■ High Performance, Low Power AVR? 8-Bit Microcontroller
■ Advanced RISC Architecture
–120 Powerful Instructions – Most Single
CLock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
CLock management, the reset control, the boot mode settings and the debug management. It
shows how to use the High-density and Medium-density STM32F10xxx product families and
describes the minimum hardware resources required to develop an STM32F10xxx
application.
Abstract: This application note describes how sampling CLock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling CLock and describes a method for generating a properbroadband jittered CLock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleCLock implementations.
With more and more multi-frequency CLocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a CLock line while the chip is running.
Many applications require a CLock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another CLock. This type of CLock circuit is important in
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator CLockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased CLock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At CLock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz CLock speed.
