亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

蟲蟲首頁| 資源下載| 資源專輯| 精品軟件
登錄| 注冊

CLock

  • PCA9517 Level translating I2C-

    The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the CLock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.

    標簽: translating Level 9517 PCA

    上傳時間: 2013-12-25

    上傳用戶:wsf950131

  • PCA9518 Expandable 5channel I2

    The PCA9518 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both thedata (SDA) and the CLock (SCL) lines, thus enabling virtuallyunlimited buses of 400 pF.

    標簽: Expandable 5channel 9518 PCA

    上傳時間: 2013-10-23

    上傳用戶:dumplin9

  • PCA9519 4channel level transla

    The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the CLock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.

    標簽: 4channel transla level 9519

    上傳時間: 2013-11-19

    上傳用戶:jisiwole

  • CLocking Options for Stellaris

    The main oscillator allows either a crystal or single-ended input CLock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to CLock the device after theboot process has completed.

    標簽: Stellaris CLocking Options for

    上傳時間: 2013-10-14

    上傳用戶:pol123

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, CLock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the CLock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU CLock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標簽: Signal Input Fall Rise

    上傳時間: 2013-10-23

    上傳用戶:copu

  • 介紹C16x系列微控制器的輸入信號升降時序圖及特性

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, CLock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the CLock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU CLock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.

    標簽: C16x 微控制器 輸入信號 時序圖

    上傳時間: 2014-04-02

    上傳用戶:han_zh

  • 單片機外圍線路設計

    當拿到一張CASE單時,首先得確定的是能用什么母體才能實現此功能,然后才能展開對外圍硬件電路的設計,因此首先得了解每個母體的基本功能及特點,下面大至的介紹一下本公司常用的IC:單芯片解決方案• SN8P1900 系列–  高精度 16-Bit  模數轉換器–  可編程運算放大器 (PGIA)•  信號放大低漂移: 2V•  放大倍數可編程: 1/16/64/128  倍–  升壓- 穩壓調節器 (Charge-Pump Regulator)•  電源輸入: 2.4V ~ 5V•  穩壓輸出: e.g. 3.8V at SN8P1909–  內置液晶驅動電路 (LCD Driver)–  單芯片解決方案 •  耳溫槍  SN8P1909 LQFP 80 Pins• 5000 解析度量測器 SN8P1908 LQFP 64 Pins•  體重計  SN8P1907 SSOP 48 Pins單芯片解決方案• SN8P1820 系列–  精確的12-Bit  模數轉換器–  可編程運算放大器 (PGIA)• Gain Stage One: Low Offset 5V, Gain: 16/32/64/128• Gain Stage One: Low Offset 2mV, Gain: 1.3 ~ 2.5–  升壓- 穩壓調節器•  電源輸入: 2.4V ~ 5V•  穩壓輸出: e.g. 3.8V at SN8P1829–  內置可編程運算放大電路–  內置液晶驅動電路 –  單芯片解決方案 •  電子醫療器 SN8P1829 LQFP 80 Pins 高速/低功耗/高可靠性微控制器• 最新SN8P2000 系列– SN8P2500/2600/2700 系列– 高度抗交流雜訊能力• 標準瞬間電壓脈沖群測試 (EFT): IEC 1000-4-4• 雜訊直接灌入芯片電源輸入端• 只需添加1顆 2.2F/50V 旁路電容• 測試指標穩超 4000V (歐規)– 高可靠性復位電路保證系統正常運行• 支持外部復位和內部上電復位• 內置1.8V 低電壓偵測可靠復位電路• 內置看門狗計時器保證程序跳飛可靠復位– 高抗靜電/栓鎖效應能力– 芯片工作溫度有所提高: -200C ~ 700C     工規芯片溫度: -400C ~ 850C 高速/低功耗/高可靠性微控制器• 最新 SN8P2000 系列– SN8P2500/2600/2700 系列– 1T  精簡指令級結構• 1T:  一個外部振蕩周期執行一條指令•  工作速度可達16 MIPS / 16 MHz Crystal–  工作消耗電流 < 2mA at 1-MIPS/5V–  睡眠模式下消耗電流 < 1A / 5V額外功能• 高速脈寬調制輸出 (PWM)– 8-Bit PWM up to 23 KHz at 12 MHz System CLock– 6-Bit PWM up to 93 KHz  at 12 MHz System CLock– 4-Bit PWM up to 375 KHz  at 12 MHz System CLock• 內置高速16 MHz RC振蕩器 (SN8P2501A)• 電壓變化喚醒功能• 可編程控制沿觸發/中斷功能– 上升沿 / 下降沿 / 雙沿觸發• 串行編程接口

    標簽: 單片機 線路設計

    上傳時間: 2013-10-21

    上傳用戶:jiahao131

  • 用單片機配置FPGA—PLD設計技巧

    用單片機配置FPGA—PLD設計技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is CLocking in ONE BITof configuration data per CLock–start from the BIT 0􀂄The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*CLock = 122,880CLock•assume the CLock is 4MHz•122,880*1/4Mhz=30.72msec

    標簽: FPGA PLD 用單片機 設計技巧

    上傳時間: 2013-10-09

    上傳用戶:a67818601

  • Xilinx UltraScale:新一代架構滿足您的新一代架構需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system CLocks, reducing CLock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標簽: UltraScale Xilinx 架構

    上傳時間: 2013-11-13

    上傳用戶:瓦力瓦力hong

  • XAPP806 -決定DDR反饋時鐘的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback CLock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output CLock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    標簽: XAPP 806 DDR DCM

    上傳時間: 2013-10-15

    上傳用戶:euroford

亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频
国产日韩综合一区二区性色av| 亚洲影院色无极综合| 麻豆av一区二区三区| 亚洲人成亚洲人成在线观看图片| 国产精品婷婷午夜在线观看| 欧美日韩国产不卡| 模特精品在线| 嫩草国产精品入口| 欧美/亚洲一区| 欧美www视频| 欧美风情在线| 在线性视频日韩欧美| 久久综合免费视频影院| 国产原创一区二区| 久久久久久电影| 欧美搞黄网站| 性做久久久久久免费观看欧美| 亚洲国产一区视频| 蜜臀av国产精品久久久久| 伊人一区二区三区久久精品| 久久大逼视频| 精久久久久久| 免费观看成人网| 在线欧美一区| 久久综合影视| 亚洲精品久久嫩草网站秘色 | 蜜桃久久精品一区二区| 亚洲电影在线免费观看| 国产精品青草久久久久福利99| 亚洲精品日日夜夜| 国产在线不卡视频| 亚洲免费高清视频| 欧美日韩一区在线| 亚洲免费小视频| 国产亚洲a∨片在线观看| 久久久久99精品国产片| 国产香蕉97碰碰久久人人| 免费91麻豆精品国产自产在线观看| 久久国产日韩| 在线成人激情| 欧美国产综合一区二区| 亚洲激情女人| 欧美精品18| 136国产福利精品导航网址应用| 亚洲欧美中文字幕| 欧美午夜精品久久久久久久| 一区二区亚洲精品| 久久米奇亚洲| 久久久久久久成人| 欧美激情第六页| 欧美在线视频一区二区三区| 国产精品一级在线| 欧美精品播放| 亚洲电影免费观看高清| 久久久久这里只有精品| 亚洲女ⅴideoshd黑人| 影音国产精品| 国产精品视频一二三| 国产精品视频导航| 欧美日本国产视频| 亚洲国产导航| 日韩网站在线看片你懂的| 欧美在线播放视频| 亚洲国产99精品国自产| 国产精品v亚洲精品v日韩精品 | 欧美aaa级| 亚洲午夜久久久久久久久电影院 | 最新国产精品拍自在线播放| 欧美特黄一级大片| 六月婷婷一区| 欧美一区亚洲二区| 在线视频亚洲| 亚洲日本va在线观看| 国产欧美日韩免费| 欧美日韩一区在线观看视频| 久久久久久久综合狠狠综合| 夜夜爽www精品| 一色屋精品视频免费看| 国产精品日日摸夜夜摸av| 欧美精品二区| 麻豆国产精品一区二区三区| 一区二区三区久久网| 国产欧美一级| 久久综合精品国产一区二区三区| 亚洲成色777777在线观看影院| 欧美日韩亚洲精品内裤| 狼人天天伊人久久| 欧美一区二区视频网站| 欧美www视频| 久久久久久夜精品精品免费| 亚洲欧美制服中文字幕| 在线亚洲电影| 一本久久知道综合久久| 亚洲经典三级| 亚洲国产精品一区二区久| 精品999在线观看| 久久久久国产精品一区| 午夜精品久久久| 亚洲综合第一页| 国产夜色精品一区二区av| 久久亚洲风情| 欧美一级黄色网| 99在线精品免费视频九九视| 国内成人在线| 国产视频一区三区| 欧美午夜美女看片| 国产麻豆成人精品| 激情六月综合| 国内视频一区| 狠狠色丁香久久综合频道| 国产日韩在线播放| 国产女精品视频网站免费 | 国产精品一区二区三区四区五区| 欧美日韩三区| 欧美午夜精品久久久久久浪潮 | 久久久久久久久久久久久女国产乱| 午夜精品免费视频| 午夜精品视频一区| 久久精品九九| 久久综合狠狠综合久久激情| 老巨人导航500精品| 欧美大片va欧美在线播放| 欧美经典一区二区| 欧美午夜国产| 国产精品久久久久久久久果冻传媒 | 亚洲一区二区三区免费观看| 一区二区三区不卡视频在线观看 | 亚洲欧美国产不卡| 午夜老司机精品| 欧美一级大片在线观看| 欧美在线关看| 免费成人在线观看视频| 欧美日韩国产在线看| 国产精品婷婷午夜在线观看| 国内成+人亚洲+欧美+综合在线| 亚洲第一区在线| 在线综合亚洲欧美在线视频| 亚洲欧美一区二区三区极速播放| 久久久久欧美精品| 欧美精品日韩www.p站| 国产精一区二区三区| 伊人久久男人天堂| 美女精品自拍一二三四| 欧美成人免费播放| 亚洲成人自拍视频| 亚洲国产精品久久精品怡红院| 影音先锋中文字幕一区| 在线综合+亚洲+欧美中文字幕| 亚洲特黄一级片| 欧美风情在线| 国内精品伊人久久久久av影院| 亚洲精品美女在线观看| 午夜久久99| 国产精品永久免费| 欧美理论视频| 国产丝袜一区二区| 99国产精品99久久久久久粉嫩| 亚洲一区精品电影| 噜噜噜躁狠狠躁狠狠精品视频| 欧美日韩一区二区视频在线观看| 国产精品欧美久久| 亚洲黄色小视频| 欧美一区视频| 欧美调教视频| 在线日韩一区二区| 欧美日韩免费视频| 狠久久av成人天堂| 亚洲欧美日韩国产中文| 欧美精品在线免费| 在线精品福利| 欧美专区一区二区三区| 欧美午夜在线| 亚洲精品欧美专区| 免费在线亚洲欧美| 国产亚洲福利| 亚洲免费小视频| 欧美日韩在线视频观看| 亚洲国产一成人久久精品| 欧美亚洲自偷自偷| 欧美精品在线极品| 亚洲国产精品国自产拍av秋霞| 欧美在线短视频| 国产精品免费区二区三区观看| 亚洲美女诱惑| 欧美丰满高潮xxxx喷水动漫| 激情伊人五月天久久综合| 午夜一区二区三区不卡视频| 欧美日韩天堂| 99精品国产在热久久下载| 欧美成人a∨高清免费观看| 国内自拍亚洲| 欧美一区二区三区视频在线| 国产精品扒开腿做爽爽爽软件| 亚洲精品视频一区| 免费视频亚洲| 亚洲国产成人av| 美玉足脚交一区二区三区图片| 国语对白精品一区二区| 欧美一区二区大片| 国产婷婷色一区二区三区四区|