This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, CLocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.
標(biāo)簽： Integrated Digital Circuit Design
上傳時(shí)間： 2013-11-04
上傳用戶：life840315
A tutorial on SAR type A/D converters, this note contains detailed information on several 12-bit circuits. Comparator, CLocking, and preamplifier designs are discussed. A final circuit gives a 12-bit conversion in 1.8µs. Appended sections explain the basic SAR technique and explore D/A considerations.
標(biāo)簽： 逐次逼近 AD轉(zhuǎn)換器
上傳時(shí)間： 2014-01-21
上傳用戶：釣鰲牧馬
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.
標(biāo)簽： Stellaris CLocking Options for
上傳時(shí)間： 2013-10-14
上傳用戶：pol123
用單片機(jī)配置FPGA—PLD設(shè)計(jì)技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is CLocking in ONE BITof configuration data per CLOCK–start from the BIT 0The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*clock = 122,880Clock•assume the CLOCK is 4MHz•122,880*1/4Mhz=30.72msec
標(biāo)簽： FPGA PLD 用單片機(jī) 設(shè)計(jì)技巧
上傳時(shí)間： 2013-10-09
上傳用戶：a67818601
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum CLocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2014-12-28
上傳用戶：yan2267246
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific CLocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時(shí)間： 2013-11-01
上傳用戶：truth12
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum CLocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：hjkhjk
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: CLocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)
上傳時(shí)間： 2016-05-06
上傳用戶：fagong
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and surrounding constraints for synthesis, CLocking, timing, power, test and environmental and operating conditions. SDC has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDC and numerous EDA companies have translators that can read and process SDC.
上傳時(shí)間： 2018-07-13
上傳用戶：yalsim
本文主要介紹如何在Wado設(shè)計(jì)套件中進(jìn)行時(shí)序約束，原文出自 xilinx中文社區(qū)。1 Timing Constraints in Vivado-UCF to xdcVivado軟件相比于sE的一大轉(zhuǎn)變就是約束文件，5E軟件支持的是UcF（User Constraints file，而 Vivado軟件轉(zhuǎn)換到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）標(biāo)準(zhǔn)，另外集成了Xinx的一些約束標(biāo)準(zhǔn)可以說這一轉(zhuǎn)變是xinx向業(yè)界標(biāo)準(zhǔn)的靠攏。Altera從 TimeQuest開始就一直使用SDc標(biāo)準(zhǔn)，這一改變，相信對于很多工程師來說是好事，兩個(gè)平臺之間的轉(zhuǎn)換會更加容易些。首先看一下業(yè)界標(biāo)準(zhǔn)SDc的原文介紹：Synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, CLocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
標(biāo)簽： vivado
上傳時(shí)間： 2022-03-26
上傳用戶：
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