SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, CYCLONE, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck
標簽：
controller
written
NIOS2
using
上傳時間：
2016-08-12
上傳用戶：王楚楚
