中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing Capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-Capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system Capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-07
上傳用戶：songrui
為滿足無(wú)線網(wǎng)絡(luò)技術(shù)具有低功耗、節(jié)點(diǎn)體積小、網(wǎng)絡(luò)容量大、網(wǎng)絡(luò)傳輸可靠等技術(shù)要求，設(shè)計(jì)了一種以MSP430單片機(jī)和CC2420射頻收發(fā)器組成的無(wú)線傳感節(jié)點(diǎn)。通過(guò)分析其節(jié)點(diǎn)組成，提出了ZigBee技術(shù)中的幾種網(wǎng)絡(luò)拓?fù)湫问剑⒀芯苛薢igBee路由算法。針對(duì)不同的傳輸要求形式選用不同的網(wǎng)絡(luò)拓?fù)湫问娇梢员M大可能地減少系統(tǒng)成本。同時(shí)針對(duì)不同網(wǎng)絡(luò)選用正確的ZigBee路由算法有效地減少了網(wǎng)絡(luò)能量消耗，提高了系統(tǒng)的可靠性。應(yīng)用試驗(yàn)表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統(tǒng)的有線通信方式相比可以節(jié)約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large Capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
標(biāo)簽： ZigBee 無(wú)線傳感網(wǎng)絡(luò) 協(xié)議研究 路由
上傳時(shí)間： 2013-10-09
上傳用戶：robter
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing Capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-Capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system Capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-05
上傳用戶：超凡大師
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load and, To simplify the design of complex Internet services. SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service Capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.
標(biāo)簽： Event-Driven Architecture Internet building
上傳時(shí)間： 2015-09-28
上傳用戶：日光微瀾
Beginning with an overview of SQL Server 2000, this book discusses online transaction processing (OLTP) and online analytical processing (OLAP), features a tour of different SQL Server releases, and offers a guide to installation. The author describes and demonstrates the changes since SQL Server 7.0, thoroughly exploring SQL Server 2000 s Capacity as a Web-enabled database server. Readers are then immersed in advanced database administration topics such as performance optimization and debugging techniques.
標(biāo)簽： transaction processing Beginning discusses
上傳時(shí)間： 2013-11-28
上傳用戶：eclipse
C procedures commonly used algorithm sets. Common C language code link. Contact enhancement of the C language code Capacity.
標(biāo)簽： enhancement procedures algorithm commonly
上傳時(shí)間： 2013-12-23
上傳用戶：變形金剛
Foreword The four case studies that follow each have a number of common features. They each illustrate the birth of an idea and show how that idea can be realised into a marketable product. Each case study deals with engineering design and development issues and each highlights the importance of developing sound marketing strategies including market research. The importance of appropriate support mechanisms for young entrepreneurs is also covered. The case studies illustrate how successful entrepreneurs deploy a range of entrepreneurial skills and know-how. Above all, the entrepreneurs are seen to have the Capacity to innovate and exercise vision. We are grateful to Liz Read, Development Manager for Enterprise and Entrepreneurship (Students) at Coventry University for providing these case studies.
標(biāo)簽： each Foreword features studies
上傳時(shí)間： 2016-02-17
上傳用戶：熊少鋒
Application Note Abstract This Application Note introduces a complete and detailed PSoC® project. Telephone Call Logger keeps the detailed record of approximately 945 phone calls (7-digit number is assumed to be one phone call) including date, start time and the duration of the phone call in the PSoC device. Users can get this detailed report into the PC environment by using free software, which is included in the project file. When records reach near full Capacity of the Flash memory, an LED will turn on to show that it is necessary to backup the data. Software gets the data from PSoC, organizes it and prepares a printable version. Additionally, it sends the date and time information to the PSoC. The external parts in this project can be obtained easily in the market.
標(biāo)簽： Application Note introduces Abstract
上傳時(shí)間： 2014-01-01
上傳用戶：集美慧
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