The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On ResetCircuit protects the internal logic against powering up in the wrongstate.
上傳時間： 2013-11-20
上傳用戶：ynzfm
根據看門狗電路的原理，設計出簡單適用、性能可靠的1TrL型看門狗電路以及價格低廉、性能可靠的微功耗CMOS型看門狗電路，同時還介紹了常用的uP監視器O型看門狗電路。關鍵詞：看門狗電路；1TrL型；CMOS型Abstract：In accordance with the principle of WDT (Watch Dog Timer 1Circuit，design a，IT．L type WTD Circuit，it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD Circuit，it is low prices and mini-power consumption。Also the article describes a common uP type WTD Circuit。Key word：WDT Circuit；TFL type；CMOS typ e
上傳時間： 2013-11-05
上傳用戶：685
This document describes the system hardware implementation for the OMAP3530 processor and theTPS65930/20 companion power integrated Circuit (IC). The document concentrates on the powerconnectivity for the processor and the companion power IC. The document also briefly explains someother specifics related to power, such as the boot modes and the power-up sequence.
上傳時間： 2013-11-14
上傳用戶：yeling1919
本文介紹了一種基于單片機的健身車轉速測量系統。該系統具有電路簡單、使用方便等特點。文中詳細介紹了該系統的工作原理,并且給出了它的硬件原理圖和軟件設計程序框圖。關鍵詞:轉速 單片機 測量ABSTRACT :This paper introduces a measuring system of the rotational velocity of exercise bike based on single - chip microcomputer . It has such advantages : simple Circuit ,convenient use and so on. The work principle is presented in detail in this paper and the block diagram of hardware and program flow chart are giv2 en as well .KEYWORDS :Rotational velocity Single - chip microcomputer Measuring
上傳時間： 2013-11-02
上傳用戶：源弋弋
The PCA9516 is a BiCMOS integrated Circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上傳時間： 2013-11-21
上傳用戶：q123321
The PCA9517 is a CMOS integrated Circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
The PCA9518 is a BiCMOS integrated Circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both thedata (SDA) and the clock (SCL) lines, thus enabling virtuallyunlimited buses of 400 pF.
標簽： Expandable 5channel 9518 PCA
上傳時間： 2013-10-23
上傳用戶：dumplin9
The PCA9557 is a silicon CMOS Circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
上傳時間： 2014-01-18
上傳用戶：bs2005
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator Circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.
標簽： Stellaris Clocking Options for
上傳時間： 2013-10-14
上傳用戶：pol123
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump Circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標簽： MULTICHANNEL 5.5 TO RS
上傳時間： 2013-10-19
上傳用戶：ddddddd
