Fast Fourier Transform power point The rectangular window introduces broadening of any frequency components [`smearing鈥? and sidelobesthat may overlap with other frequency components [`leakage鈥?. 鈥he effect improves as Nincreases 鈥owever, the rectangle window has poor properties and better choices of wncan lead to better spectral properties [less leakage, in particular] 鈥搃.e. instead of just truncating the summation, we can pre-multiply by a suitable window function wnthat has better frequency domain properties. 鈥ore on window design in the filter design section of the course
標簽： rectangular introduces broadening Transform
上傳時間： 2017-03-25
上傳用戶：change0329
Socket progrm make the IP and Port in listening mode.It work as server, and number of clients can connect with this application
標簽： and listening clients Socket
上傳時間： 2013-12-19
上傳用戶：guanliya
經典英文原版PHP教程networking, data structures, regular expressions, math, configuration, graphics, MySQL/PostgreSQL support, XML, algorithms, debugging, optimization...and 650 downloadable code examples, with a Foreword by PHP 5 contributor and Zend Engine 2 co-creator Andi Gutmans!
標簽： configuration expressions networking structures
上傳時間： 2014-01-28
上傳用戶：cuibaigao
個人時間管理的很好的表格，從英國網站下來的。網址organizeit.co.uk
上傳時間： 2013-12-22
上傳用戶：gundamwzc
Advanced ASIC Chip Synthesis Using Synopsys Design Compiler. This second edition of this book describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
標簽： Synthesis Advanced Synopsys Compiler
上傳時間： 2017-04-04
上傳用戶：lanwei
this is a graphical editor which is similar to MS-PAINT done using c-language runs on turbo c/c++ compiler.
標簽： c-language graphical MS-PAINT similar
上傳時間： 2017-04-06
上傳用戶：yepeng139
VMEbus slave architecture source code Can be implemented on the slave board of a chasis as slave controller
標簽： slave architecture implemented VMEbus
上傳時間： 2017-04-12
上傳用戶：遠遠ssad
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標簽： increasingly description designing languages
上傳時間： 2014-01-08
上傳用戶：小草123
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4- bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E58B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security
標簽： microcontroller programmable in-system W78E58B
上傳時間： 2017-04-27
上傳用戶：yiwen213
A few drivers for the Motorola C380 s celluar phone hardware with a simple test application. It s configured to build a binary that is to be uploaded at 0x03fd0000 and run at 0x03fd0010
標簽： application Motorola hardware drivers
上傳時間： 2017-05-01
上傳用戶：zhangzhenyu
