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Co-Verification

編寫testbench的超好教程

編寫testbench的超好教程，網上這種資料比較少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf

標簽： testbench 編寫教程

上傳時間： 2014-01-05

上傳用戶：Miyuki
The package contains a Reed-Solomon coding and decoding program, derived partly from Phil Karn/Rob

The package contains a Reed-Solomon coding and decoding program, derived partly from Phil Karn/Robert Morelos-Zaragoza "new_rs_erasures.c". In particular the Berlekamp-Massey algorithm has not been modified. New features compared to "new_rs_erasures.c" are: - fully parameterized: code parameters (n,k,m) can be selected via command line options. - decoding optional by Euclid or Belekamp-Massey algorithm - efficient support of shortened codes - extensive verbose levels for hardware verification

標簽： Reed-Solomon contains decoding package

上傳時間： 2013-12-11

上傳用戶：shinesyh
dephi OBD II 技術路線,所謂OBD-II是一個系列的法規

dephi OBD II 技術路線,所謂OBD-II是一個系列的法規，目的是通過檢測整個動力總成系統的故障或劣化來減少在用車的排放，排放控制系統是OBD-II的基礎。OBD-II同時也提供診斷的標準化，修理及其他相關服務的標準化。當車輛的排放（HC,CO,NOx)由于被檢測的零部件/系統的劣化而超出相關標準的1.5倍時，故障指示燈（MIL）必須被點亮以通知駕駛員，并同時記錄故障碼。

標簽： OBD-II dephi OBD II

上傳時間： 2016-07-03

上傳用戶：refent
此軟件功能強大 It operates in the highly ompetitive UK banking sector against ...barcode reader to reduce h

此軟件功能強大 It operates in the highly ompetitive UK banking sector against ...barcode reader to reduce human errors in the ordering process. - The ...co-generation and unit- testing of client and server components of the

標簽： ompetitive operates banking against

上傳時間： 2014-11-29

上傳用戶：huyiming139
Neural network match filter of chirp pulse compression Neural network match filter of chirp pulse co

Neural network match filter of chirp pulse compression Neural network match filter of chirp pulse compression

標簽： network Neural filter match

上傳時間： 2014-02-23

上傳用戶：ikemada
Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM RISC processor

Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM RISC processor. It features a on-chip biometric engine performing enrollment verification and identification, an internal record cache of up to 25 records and a secure command protocol over USB, SPI, UART. This protocol enables an external host system or processor to control the onchip bioengine functions, manipulate the record cache, and securely export record cache records for external storage. Together with the FingerChip sensor device AT77C104B, it forms an embedded, secured biometric turnkey solution.

標簽： processor FingerChip pincount Atmel

上傳時間： 2013-12-26

上傳用戶：shawvi
This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming boo

This a very simple baseband simulator for SC-FDMA system. This simulator is part of the upcoming book “Single Carrier FDMA: A New Air Interface for Long Term Evolution” (Wiley, Nov. 2008) which I co-authored with professor David J. Goodman at Polytechnic University. The purpose of this simulator is to give some concrete idea of how SC-FDMA system works. It does lack many realistic and sophisticated features such as channel coding, time-varying fading channel model, soft decision decoding, etc. Regardless, I am hoping that it will help you understand SC-FDMA which is a fairly new development in 3GPP LTE.

標簽： simulator This baseband upcoming

上傳時間： 2016-08-26

上傳用戶：小草123
In the previous article, we presented an approach for capturing similarity between words that was co

In the previous article, we presented an approach for capturing similarity between words that was concerned with the syntactic similarity of two strings. Today we are back to discuss another approach that is more concerned with the meaning of words. Semantic similarity is a confidence score that reflects the semantic relation between the meanings of two sentences. It is difficult to gain a high accuracy score because the exact semantic meanings are completely understood only in a particular context.

標簽： similarity presented capturing previous

上傳時間： 2013-12-13

上傳用戶：wcl168881111111
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation

A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.

標簽： simulation Verilog writing clock

上傳時間： 2016-10-12

上傳用戶：王者A
A code writing by Verilog which can find medium value. With a C file to see the simulation results.

A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.

標簽： simulation Verilog writing results

上傳時間： 2014-11-18

上傳用戶：ljt101007