Programming - Verilog VHDL Golden Reference Guide DOULOS Church Hatch, 22 Market Place, Ringwood. Hampshire. BH24 1AW England. Tel (+44) (0)1425 471223 Fax (+44) (0)1425 471573 Email info@doulos.co.uk URL http://www.doulos.co.uk
標(biāo)簽： Programming Reference Ringwood Verilog
上傳時(shí)間： 2017-05-12
上傳用戶(hù)：ainimao
dear ahmedmgera you are welcome, to start activity you need to Introduce Yourself and Get 10 Coins & I Mana
標(biāo)簽： ahmedmgera Introduce you activity
上傳時(shí)間： 2014-11-26
上傳用戶(hù)：zaizaibang
Beamforming thesis describing Study of a various Beamforming Techniques And Implementation of the Constrained Least Mean Squares (LMS) algorithm for Beamforming
標(biāo)簽： Beamforming Implementation describing Techniques
上傳時(shí)間： 2013-12-25
上傳用戶(hù)：wuyuying
This library implements the KLT Tracking algorithm [2004] for Feature Tracking in Video useful in computer vision tasks like object recognition, image indexing, tracking and structure from motion. This implementation uses programmable Graphics Hardware to achieve considerable speedup in the running time of the GPU-based implementation.
標(biāo)簽： Tracking implements algorithm Feature
上傳時(shí)間： 2013-12-10
上傳用戶(hù)：trepb001
This library implements the KLT Tracking algorithm [2004] for Feature Tracking in Video useful in computer vision tasks like object recognition, image indexing, tracking and structure from motion. This implementation uses programmable Graphics Hardware to achieve considerable speedup in the running time of the GPU-based implementation.
標(biāo)簽： Tracking implements algorithm Feature
上傳時(shí)間： 2013-12-19
上傳用戶(hù)：WMC_geophy
The VHDL book http://www.onlinefreeebooks.net/engineering-ebooks/electrical-engineering/the-vhdl-cookbook-pdf.html
標(biāo)簽： electrical-engineering engineering-ebooks onlinefreeebooks the-vhdl-co
上傳時(shí)間： 2014-01-07
上傳用戶(hù)：love1314
PARALLEL PORT JTAG PROGRAMMER Adaptor used to program the S3C2410 samsung processor. The rar file contains PDF and DSN format circuit diagram. This can be used and to make your own parallel port wiggler programmer
標(biāo)簽： PROGRAMMER processor PARALLEL Adaptor
上傳時(shí)間： 2013-12-05
上傳用戶(hù)：zhangzhenyu
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
標(biāo)簽： application real-time Synopsys emphasis
上傳時(shí)間： 2017-07-05
上傳用戶(hù)：waitingfy
WordWeb thesaurus/dictionary component for Delphi and C++ Builder Version 1.62, freeware The component uses the free WordWeb thesaurus/dictionay available from http://wordweb.co.uk/free You (and anyone using your program) should install WordWeb before using this component. If it is not installed the component raises an exception when you look up a word. It will also work with WordWeb Pro, available from http://www.wordweb.co.uk/ For more flexible and customizable dictionary/thesaurus components see WordWeb Developer at http://www.x-word.com/wwdev/
標(biāo)簽： dictionary thesaurus component freeware
上傳時(shí)間： 2014-01-11
上傳用戶(hù)：talenthn
移位運(yùn)算器SHIFTER 使用Verilog HDL 語(yǔ)言編寫(xiě)，其輸入輸出端分別與鍵盤(pán)/顯示器LED 連接。移位運(yùn)算器是時(shí)序電路，在J鐘信號(hào)到來(lái)時(shí)狀態(tài)產(chǎn)生變化， CLK 為其時(shí)鐘脈沖。由S0、S1 、M 控制移位運(yùn)算的功能狀態(tài)，具有數(shù)據(jù)裝入、數(shù)據(jù)保持、循環(huán)右移、帶進(jìn)位循環(huán)右移，循環(huán)左移、帶進(jìn)位循環(huán)左移等功能。 CLK 是時(shí)鐘脈沖輸入，通過(guò)鍵5 產(chǎn)生高低電平M 控制工作模式， M=l 時(shí)帶進(jìn)位循環(huán)移位，由鍵8 控制CO 為允許帶進(jìn)位移位輸入，由鍵7 控制:S 控制移位模式0-3 ，由鍵6 控制，顯示在數(shù)碼管LED8 上 D[7..0]是移位數(shù)據(jù)輸入，由鍵2 和1 控制，顯示在數(shù)碼管2 和1 上 QB[7..0]是移位數(shù)據(jù)輸出，顯示在數(shù)碼管6 和5 上:cn 是移位數(shù)據(jù)輸出進(jìn)位，顯示在數(shù)碼管7 上。
標(biāo)簽： SHIFTER Verilog HDL 移位
上傳時(shí)間： 2014-01-16
上傳用戶(hù)：wys0120
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