并行計算的英文教程 Parallel Computation Architecture, Algorithm and Programming
標簽： Architecture Computation Programming Algorithm
上傳時間： 2016-12-31
上傳用戶：lo25643
Computation on GPUs: From A Programmable Pipeline to an Efficient Stream Processor
標簽： Programmable Computation Efficient Processor
上傳時間： 2017-01-18
上傳用戶：330402686
FRFT時頻變換代碼（參考算法：H.M. Ozaktas, M.A. Kutay, and G. Bozdagi.Digital Computation of the fractional Fourier transform.IEEE Trans. Sig. Proc., 44:2141--2150, 1996.）
標簽： H.M. G. M.A. Computation
上傳時間： 2013-12-21
上傳用戶：希醬大魔王
Shows how Linux futex syscall can be used to distribute Computation to multiple threads.
標簽： Computation distribute multiple syscall
上傳時間： 2017-02-20
上傳用戶：dave520l
This the Firmware code for the ADE7758 for the PIC Micro controller for the Computation of three phase parameters.
標簽： the for Computation controller
上傳時間： 2017-04-01
上傳用戶：lanwei
Mutual Information Computation
標簽： Information Computation Mutual
上傳時間： 2014-01-09
上傳用戶：z754970244
for parallel Computation
標簽： Computation parallel for
上傳時間： 2013-11-25
上傳用戶：cmc_68289287
在理論分析循環碼編碼和譯碼基本原理的基礎上，提出了基于單片機系統的(24，16)循環碼軟件實現編碼、譯碼的方案。仿真結果表明(24，16)循環碼能有效地克服來自通訊信道的干擾，保證數據通信的可靠及系統的穩定，使誤碼率大幅度降低。本論文對(24，16)循環碼的研究結果表明，可以有效地降低錯誤概率和提高系統的吞吐量，實現糾錯僅需要在接收端增加有限的存儲空間和計算復雜度，具有一定的實用價值。 Abstract: Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and Computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.
上傳時間： 2013-11-09
上傳用戶：gaoliangncepu
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andComputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時間： 2013-11-07
上傳用戶：swing
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and Computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
