Typical industrial and automotive applications requiremultiple high current, low voltage power supply solutionsto drive everything from disc drives to microprocessors.For many of these applications, particularly thosethat have size Constraints, the LT3501® dual step-downconverter is an attractive solution because it’s compactand inexpensive compared to a 2-chip solution. The dualconverter accommodates a 3V to 25V input voltage rangeand is capable of supplying up to 3A per channel. Thecircuit in Figure 1 produces 3.3V and 1.8V.
上傳時間： 2014-12-24
上傳用戶：372825274
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the Constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時間： 2013-11-01
上傳用戶：truth12
15.2 已經加入了有關貫孔及銲點的Z軸延遲計算功能. 先開啟 Setup - Constraints - Electrical constraint sets 下的 DRC 選項. 點選 Electrical Constraints dialog box 下 Options 頁面 勾選 Z-Axis delay欄.
上傳時間： 2013-11-12
上傳用戶：Late_Li
通用陣列邏輯GAL實現基本門電路的設計 一、實驗目的 1.了解GAL22V10的結構及其應用； 2.掌握GAL器件的設計原則和一般格式； 3.學會使用VHDL語言進行可編程邏輯器件的邏輯設計； 4.掌握通用陣列邏輯GAL的編程、下載、驗證功能的全部過程。 二、實驗原理 1. 通用陣列邏輯GAL22V10 通用陣列邏輯GAL是由可編程的與陣列、固定（不可編程）的或陣列和輸出邏輯宏單元（OLMC）三部分構成。GAL芯片必須借助GAL的開發軟件和硬件，對其編程寫入后，才能使GAL芯片具有預期的邏輯功能。GAL22V10有10個I/O口、12個輸入口、10個寄存器單元，最高頻率為超過100MHz。 ispGAL22V10器件就是把流行的GAL22V10與ISP技術結合起來，在功能和結構上與GAL22V10完全相同，并沿用了GAL22V10器件的標準28腳PLCC封裝。ispGAl22V10的傳輸時延低于7.5ns，系統速度高達100MHz以上，因而非常適用于高速圖形處理和高速總線管理。由于它每個輸出單元平均能夠容納12個乘積項，最多的單元可達16個乘積項，因而更為適用大型狀態機、狀態控制及數據處理、通訊工程、測量儀器等領域。ispGAL22V10的功能框圖及引腳圖分別見圖1-1和1-2所示。 另外，采用ispGAL22V10來實現諸如地址譯碼器之類的基本邏輯功能是非常容易的。為實現在系統編程，每片ispGAL22V10需要有四個在系統編程引腳，它們是串行數據輸入(SDI)，方式選擇(MODE)、串行輸出(SDO)和串行時鐘(SCLK)。這四個ISP控制信號巧妙地利用28腳PLCC封裝GAL22V10的四個空腳，從而使得兩種器件的引腳相互兼容。在系統編程電源為+5V，無需外接編程高壓。每片ispGAL22V10可以保證一萬次在系統編程。 ispGAL22V10的內部結構圖如圖1-3所示。 2.編譯、下載源文件 用VHDL語言編寫的源程序，是不能直接對芯片編程下載的，必須經過計算機軟件對其進行編譯，綜合等最終形成PLD器件的熔斷絲文件(通常叫做JEDEC文件，簡稱為JED文件)。通過相應的軟件及編程電纜再將JED數據文件寫入到GAL芯片，這樣GAL芯片就具有用戶所需要的邏輯功能。 3.工具軟件ispLEVER簡介 ispLEVER 是Lattice 公司新推出的一套EDA軟件。設計輸入可采用原理圖、硬件描述語言、混合輸入三種方式。能對所設計的數字電子系統進行功能仿真和時序仿真。編譯器是此軟件的核心，能進行邏輯優化，將邏輯映射到器件中去，自動完成布局與布線并生成編程所需要的熔絲圖文件。軟件中的Constraints Editor工具允許經由一個圖形用戶接口選擇I/O設置和引腳分配。軟件包含Synolicity公司的“Synplify”綜合工具和Lattice的ispVM器件編程工具，ispLEVER軟件提供給開發者一個簡單而有力的工具。
上傳時間： 2013-11-17
上傳用戶：看到了沒有
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and Constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout Constraints where bulleted items at the beginning of a topic highlight important Constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
This a GA implementation using binary and real coded variables. Mixed variables can be used. Constraints can also be handled. All Constraints must be greater-than-equal-to type (g >= 0) and normalized (see the sample problem in prob1 in objective()).
標簽： variables implementation Constra binary
上傳時間： 2015-03-16
上傳用戶：qiao8960
內容如下： 1.The history of the computerized database 2.SQL Data Statements--those used to create, manipulate, and retrieve data stored in your database example statements include select, update, insert, and delete 3.SQL Schema Statements--those used to create database objects, such as tables, indexes, and Constraints 4.How data sets can interact with queries 5.The importance of subqueries 6.Data conversion and manipulation via SQL s built-in functions 7.How conditional logic can be used in Data Statements
標簽： computerized Statements database history
上傳時間： 2015-04-25
上傳用戶：ardager
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing Constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標簽： the Analyzer Compiler project
上傳時間： 2013-12-19
上傳用戶：Yukiseop
Problem Statement You are given a string input. You are to find the longest substring of input such that the reversal of the substring is also a substring of input. In case of a tie, return the string that occurs earliest in input. Definition Class: ReverseSubstring Method: findReversed Parameters: string Returns: string Method signature: string findReversed(string input) (be sure your method is public) Notes The substring and its reversal may overlap partially or completely. The entire original string is itself a valid substring (see example 4). Constraints input will contain between 1 and 50 characters, inclusive. Each character of input will be an uppercase letter ( A - Z ). Examples 0) "XBCDEFYWFEDCBZ" Returns: "BCDEF" We see that the reverse of BCDEF is FEDCB, which appears later in the string. 1)
上傳時間： 2015-09-21
上傳用戶：sunjet
Embedded computer systems permeate all aspects of our daily lives. Alarm clocks, coffee makers, digital watches, cell phones, and automobiles are just a few of the devices that make use of embedded systems. The design and development of such systems is unique, because the design Constraints are different for each system. Essential to the development of an embedded system is an understanding of the hardware and software used for development.
標簽： Embedded computer permeate aspects
上傳時間： 2013-12-15
上傳用戶：erkuizhang
