The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上傳時間： 2013-11-21
上傳用戶：q123321
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
上傳時間： 2014-12-28
上傳用戶：nshark
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上傳時間： 2013-10-09
上傳用戶：3294322651
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標簽： 4channel multiple 9544A 9544
上傳時間： 2014-12-28
上傳用戶：潛水的三貢
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register. Two interrupt inputs, INT0 and INT1, one for each of theSCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as anAND of the two interrupt inputs, is provided.
上傳時間： 2013-12-07
上傳用戶：europa_lin
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
上傳時間： 2014-12-28
上傳用戶：270189020
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上傳時間： 2013-10-13
上傳用戶：bakdesec
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時間： 2013-10-11
上傳用戶：dianxin61
本文依據(jù)集成電路設(shè)計方法學，探討了一種基于標準Intel 8086 微處理器的單芯片計算機平臺的架構(gòu)。研究了其與SDRAM，8255 并行接口等外圍IP 的集成，并在對AMBA協(xié)議和8086 CPU分析的基礎(chǔ)上，采用遵從AMBA傳輸協(xié)議的系統(tǒng)總線代替?zhèn)鹘y(tǒng)的8086 CPU三總線結(jié)構(gòu)，搭建了基于8086 IP 軟核的單芯片計算機系統(tǒng)，并實現(xiàn)了FPGA 功能演示。關(guān)鍵詞：微處理器； SoC；單芯片計算機；AMBA 協(xié)議 Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
標簽： 8086 CPU 單芯片 計算機系統(tǒng)
上傳時間： 2013-12-27
上傳用戶：kernor
用單片機AT89C51改造普通雙桶洗衣機：AT89C2051作為AT89C51的簡化版雖然去掉了P0、P2等端口，使I/O口減少了，但是卻增加了一個電壓比較器，因此其功能在某些方面反而有所增強，如能用來處理模擬量、進行簡單的模數(shù)轉(zhuǎn)換等。本文利用這一功能設(shè)計了一個數(shù)字電容表，可測量容量小于2微法的電容器的容量，采用3位半數(shù)字顯示，最大顯示值為1999，讀數(shù)單位統(tǒng)一采用毫微法（nf），量程分四檔，讀數(shù)分別乘以相應的倍率。電路工作原理 本數(shù)字電容表以電容器的充電規(guī)律作為測量依據(jù)，測試原理見圖1。電源電路圖。 壓E+經(jīng)電阻R給被測電容CX充電，CX兩端原電壓隨充電時間的增加而上升。當充電時間t等于RC時間常數(shù)τ時，CX兩端電壓約為電源電壓的63.2%，即0.632E+。數(shù)字電容表就是以該電壓作為測試基準電壓，測量電容器充電達到該電壓的時間，便能知道電容器的容量。例如，設(shè)電阻R的阻值為1千歐，CX兩端電壓上升到0.632E+所需的時間為1毫秒，那么由公式τ=RC可知CX的容量為1微法。 測量電路如圖2所示。A為AT89C2051內(nèi)部構(gòu)造的電壓比較器，AT89C2051 圖2 的P1.0和P1.1口除了作I/O口外，還有一個功能是作為電壓比較器的輸入端，P1.0為同相輸入端，P1.1為反相輸入端，電壓比較器的比較結(jié)果存入P3.6口對應的寄存器，P3.6口在AT89C2051外部無引腳。電壓比較器的基準電壓設(shè)定為0.632E+，在CX兩端電壓從0升到0.632E+的過程中，P3.6口輸出為0，當電池電壓CX兩端電壓一旦超過0.632E+時，P3.6口輸出變?yōu)?。以P3.6口的輸出電平為依據(jù)，用AT89C2051內(nèi)部的定時器T0對充電時間進行計數(shù)，再將計數(shù)結(jié)果顯示出來即得出測量結(jié)果。整機電路見圖3。電路由單片機電路、電容充電測量電路和數(shù)碼顯示電路等 圖3 部分組成。AT89C2051內(nèi)部的電壓比較器和電阻R2-R7等組成測量電路，其中R2-R5為量程電阻，由波段開關(guān)S1選擇使用，電壓比較器的基準電壓由5V電源電壓經(jīng)R6、RP1、R7分壓后得到，調(diào)節(jié)RP1可調(diào)整基準電壓。當P1.2口在程序的控制下輸出高電平時，電容CX即開始充電。量程電阻R2-R5每檔以10倍遞減，故每檔顯示讀數(shù)以10倍遞增。由于單片機內(nèi)部P1.2口的上拉電阻經(jīng)實測約為200K，其輸出電平不能作為充電電壓用，故用R5兼作其上拉電阻，由于其它三個充電電阻和R5是串聯(lián)關(guān)系，因此R2、R3、R4應由標準值減去1K，分別為999K、99K、9K。由于999K和1M相對誤差較小，所以R2還是取1M。數(shù)碼管DS1-DS4、電阻R8-R14等組成數(shù)碼顯示電路。本機采用動態(tài)掃描顯示的方式，用軟件對字形碼譯碼。P3.0-P3.5、P3.7口作數(shù)碼顯示七段筆劃字形碼的輸出，P1.3-P1.6口作四個數(shù)碼管的動態(tài)掃描位驅(qū)動碼輸出。這里采用了共陰數(shù)碼管，由于AT89C2051的P1.3-P1.6口有25mA的下拉電流能力，所以不用三極管就能驅(qū)動數(shù)碼管。R8-R14為P3.0-P3.5、P3.7口的上拉電阻，用以驅(qū)動數(shù)碼管的各字段，當P3的某一端口輸出低電平時其對應的字段筆劃不點亮，而當其輸出高電平時，則對應的上拉電阻即能點亮相應的字段筆劃。
上傳時間： 2013-12-31
上傳用戶：ming529
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