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DESCRIPTION

  • AC220V轉(zhuǎn)DC5V(3W )-RS485電路-繼電器驅(qū)動(dòng)板ALTIUM設(shè)計(jì)硬件原理圖+PCB+A

    AC220V轉(zhuǎn)DC5V(3W )-RS485電路-繼電器驅(qū)動(dòng)板ALTIUM設(shè)計(jì)硬件原理圖+PCB+AD集成封裝庫,2層板設(shè)計(jì),大小為59x62mm,Altium Designer 設(shè)計(jì)的工程文件,包括完整的原理圖及PCB文件,可以用Altium(AD)軟件打開或修改,可作為你產(chǎn)品設(shè)計(jì)的參考。集成封裝器件型號(hào)列表:Library Component Count : 20Name                DESCRIPTION----------------------------------------------------------------------------------------------------CAP1                GRM21BR61A106KE19L,106,10μF,±10%,10V,X5R,0805,muRata,RoHSCON2                ConnectorCON3                ConnectorCON4                ConnectorDIODE ZENER2        SMBJ6.5CA,DO-214AA,君耀,RoHSDIODE1              1N4148,SOD-323,長(zhǎng)電,RoHSFUSE1               MST2.50,T2.5A,250V,長(zhǎng)方形,CONQUER,RoHSHEADER 5X2          HOLE - 不上螺絲     MARKER              MAX485CSA           SP485REN-L,SO-8,EXAR,RoHSNPN-1               9013,SOT-23,長(zhǎng)電,RoHSRELAY-SPST          HF46F/005-HS1,20.5×7.2×15.3mm,宏發(fā),RoHSRES-PTC             NTC,5D-9,DIP,RoHSRES2                10Ω,0603,*,RoHSRES4                471KD10,直插,君耀,RoHSZLGZY GAOYA            ZY0IFBxxP-3W        ZY0IGB05P-3W V1.00ZY_ESD-MARK

    標(biāo)簽: ac220 電路 pcb 驅(qū)動(dòng)

    上傳時(shí)間: 2021-12-21

    上傳用戶:aben

  • 黑金CYCLONE4 EP4CE6F17C8 FPGA開發(fā)板ALTIUM設(shè)計(jì)硬件工程(原理圖+PCB

    黑金CYCLONE4 EP4CE6F17C8 FPGA開發(fā)板ALTIUM設(shè)計(jì)硬件工程(原理圖+PCB+AD集成封裝庫),Altium Designer 設(shè)計(jì)的工程文件,包括完整的原理圖及PCB文件,可以用Altium(AD)軟件打開或修改,可作為你產(chǎn)品設(shè)計(jì)的參考。集成封裝器件型號(hào)列表:Library Component Count : 50Name                DESCRIPTION----------------------------------------------------------------------------------------------------1117-3.3            24LC04B_0           4148                BAV99               CAP NP_Dup2CAP NP_Dup2_1       CAP NP_Dup2_2CP2102_0            C_Dup1              C_Dup1_1C_Dup2              C_Dup3              C_Dup4              C_Dup4_1            Circuit Breaker     Circuit BreakerConnector 15        Receptacle Assembly, 15-Pin, Sim Line ConnectorDS1302_8SO          EC                  EP4CE6F17C8         Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeEP4CE6F17C8_1       Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeFuse 2              FuseHEX6HY57651620/SO_0     Header 2            Header, 2-PinHeader 9X2          Header, 9-Pin, Dual rowINDUCTOR            JTAG-10_Dup1        KEYB                LED                 LED_Dup1            M25P16-VMN3PB       16 Mb (x1) Automotive Serial NOR Flash Memory, 75 MHz, 2.7 to 3.6 V, 8-pin SO8 Narrow (MN), TubeMHDR2X20            Header, 20-Pin, Dual rowMiniUSBB            OSCPNP                 R                   RESISTOR            RN                  RN_Dup1             R_Dup1              R_Dup2              R_Dup3              R_Dup5R_Dup6              SD                  SPEAKERSRV05-4SW KEY-DPDT         ZTAbattery

    標(biāo)簽: 黑金 cyclone4 ep4ce6f17c8 fpga

    上傳時(shí)間: 2021-12-22

    上傳用戶:

  • Xilinx FPGA Virtex-7 全系列(AD集成封裝庫) IntLib后綴文件 PCB封裝

    Xilinx FPGA Virtex-7 全系列(AD集成封裝庫),IntLib后綴文件,PCB封裝帶3D視圖,拆分后文件為PcbLib+SchLib格式,Altium Designer原理圖庫+PCB封裝庫,集成封裝型號(hào)列表:Library Component Count : 157Name                DESCRIPTION----------------------------------------------------------------------------------------------------XC7V2000T-1FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commerical Grade, Pb-FreeXC7V2000T-1FHG1761I Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-1FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V2000T-1FLG1925I Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-2FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2, Commerical Grade, Pb-FreeXC7V2000T-2FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V2000T-2GFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2GFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2LFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V2000T-2LFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V585T-1FFG1157C  Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1157I  Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-1FFG1761C  Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1761I  Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-2FFG1157C  Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V

    標(biāo)簽: xilinx fpga virtex-7 封裝

    上傳時(shí)間: 2021-12-22

    上傳用戶:aben

  • Xilinx FPGA Artix-7 全系列(AD集成封裝庫) IntLib后綴文件 PCB封裝帶

    Xilinx FPGA Artix-7 全系列(AD集成封裝庫),IntLib后綴文件,PCB封裝帶3D視圖,拆分后文件為PcbLib+SchLib格式,Altium Designer原理圖庫+PCB封裝庫,集成封裝型號(hào)列表:Library Component Count : 48Name                DESCRIPTION----------------------------------------------------------------------------------------------------XC7A100T-1CSG324C   Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1CSG324I   Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG484C   Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG484I   Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG676C   Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG676I   Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FTG256C   Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FTG256I   Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-2CSG324C   Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2CSG324I   Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG484C   Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG484I   Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG676C   Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG676I   Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FTG256C   Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FTG256I   Artix-7 FPGA, 170 User I/Os, 0 GTP, 2

    標(biāo)簽: xilinx fpga

    上傳時(shí)間: 2021-12-22

    上傳用戶:

  • TMS320F28035 DSP設(shè)計(jì)的數(shù)字大功率數(shù)字化全橋變換器ALTIUM設(shè)計(jì)硬件原理圖+PCB

    基于DSP設(shè)計(jì)的數(shù)字化大功率電源數(shù)字化全橋變換器電源ALTIUM設(shè)計(jì)硬件原理圖+PCB文件,包括主板和控制板2個(gè)硬件,均為4層板設(shè)計(jì),ALTIUM設(shè)計(jì)的硬件工程文件,包括完整的原理圖和PCB文件,可以做為你的設(shè)計(jì)參考。主板原理圖器件如下:Library Component Count : 55Name                DESCRIPTION----------------------------------------------------------------------------------------------------6CWQ09F             Schottky Rectifier7416474HC16474LS1647805                7812                7815                7824                ACT45B              共模電感ARRESTER            R27030059BAV99               R26010005BRIDGE              R26060153CAPCB                  CD                  CON4                ConnectorComponent_1_1       D-1N5819            DiodeDEDIO-SMDELECTRO1            R21010742FUSE                R27010205HOLHeader 3            Header, 3-PinHeader 6            Header, 6-PinHeader 7            Header, 7-PinIR1150S             JQX-115F-I          L0                  L2                  LBAV70              R26010012LM358MOSFET N            NMOS-2              R26110100NPN                 R26080003OPTOISO1            R25030015PNP                 PNP TransistorR-NTCR20190006           R20190075R21020037           R21020037/工業(yè)B/消費(fèi)C/瓷片電容/4700pF±20%/250Vac/Y2/Y5U/引腳間距7.5mmR26020054           R26020054/工業(yè)A/消費(fèi)C/快恢復(fù)二極管/1000V/1A/1.7V/75ns/SMA/US1M-E3-61TR26030048           R26030048/工業(yè)A/消費(fèi)B/肖特基二極管/1A/100V/0.79V/SMA/SS110LR26030097           R26030097/工業(yè)B/肖特基二極管/60V/1A/0.70V/SMA/B160R29030691           R29030691/防雷接地座/最大尺寸7.36*7*10/紫銅鍍錫RES                 R20190099RES2                RES_1Res3                ResistorTL431               TRANS01TRANS7-9            Transformer         UCC3804VARISTOR            R27030060ZENERu型槽3.5x7

    標(biāo)簽: tms320f28035 dsp 全橋變換器

    上傳時(shí)間: 2021-12-22

    上傳用戶:aben

  • LTC2756 18位乘法串行輸入電流輸出數(shù)模轉(zhuǎn)換器DAC模塊ALTIUM原理圖+PCB文件

    LTC2756 18位乘法串行輸入電流輸出數(shù)模轉(zhuǎn)換器DAC模塊ALTIUM原理圖+PCB文件,硬件4層板設(shè)計(jì),大小為66mmx39mm,ALTIUM設(shè)計(jì)的工程文件,包括完整的原理圖和PCB文件,可以做為你的設(shè)計(jì)參考。 原理圖器件列表: Library Component Count : 14 Name                DESCRIPTION ---------------------------------------------------------------------------------------------------- AD8397ARDZ          Imported Capacitor           CAP.,1uF,X74,10V,10%,1206 Header 10X1 2.54 Header, 100mil, 2x1_1Header, 100mil, 2x1, Tin plated, TH Header, 100mil, 3x1 Header, 100mil, 3x1, Tin plated, TH KJDZ-2              快接端子 LT1012              LT1012 LT1360              LT1360 LTC2054_1           LTC2054 LTC2756AIG          LTC2756AIG LTC6244             Imported LTC6655             LTC6655 Resistor            RES.,1K OHMS,5%,1/16W,0603 SMA-KE              CONNECTOR, SHEILDED, END LAUNCH JACK, GOLD PLATED, FOR 0.062 PCB, EDGE MOUNTED

    標(biāo)簽: 數(shù)模轉(zhuǎn)換器

    上傳時(shí)間: 2021-12-22

    上傳用戶:

  • ABEL硬件程序設(shè)計(jì)

    硬件描述語言(英文: Hardware DESCRIPTION Language ,簡(jiǎn)稱: HDL )是電子系統(tǒng)硬件行為描述、結(jié)構(gòu)描述、數(shù)據(jù)流描述的語言。利用這種語言,數(shù)字電路系統(tǒng)的設(shè)計(jì)可以從頂層到底層(從抽象到具體)逐層描述自己的設(shè)計(jì)思想,用一系列分層次的模塊來表示極其復(fù)雜的數(shù)字系統(tǒng)。然后,利用電子設(shè)計(jì)自動(dòng)化( EDA )工具,逐層進(jìn)行仿真驗(yàn)證,再把其中需要變?yōu)閷?shí)際電路的模塊組合,經(jīng)過自動(dòng)綜合工具轉(zhuǎn)換到門級(jí)電路網(wǎng)表。接下去,再用專用集成電路 ASIC 或現(xiàn)場(chǎng)可編程門陣列 FPGA 自動(dòng)布局布線工具,把網(wǎng)表轉(zhuǎn)換為要實(shí)現(xiàn)的具體電路布線結(jié)構(gòu)

    標(biāo)簽: abel 硬件 FPGA

    上傳時(shí)間: 2021-12-24

    上傳用戶:zhanglei193

  • MICRO-USB MICRO SD卡座 HDMI DDR3 按鍵ALTIUM 集成庫(原理圖庫+3

    MICRO-USB MICRO SD卡座 HDMI DDR3 按鍵ALTIUM 集成庫(原理圖庫+3D PCB庫),.IntLib后綴文件,拆分后文件為PcbLib+SchLib格式,Altium Designer原理圖庫+PCB封裝庫,已驗(yàn)證使用,可以直接應(yīng)用到你的項(xiàng)目開發(fā)。Library Component Count : 30Name                DESCRIPTION----------------------------------------------------------------------------------------------------1_1.5KE100A_Dup1ANT                 IPEXAP2127K-ADJTRG1     STO23-5AP6212              QFN44P_120X120Banana_CPU          CAP                 CapacitorCON3                Cap Pol1            Polarized Capacitor (Radial)DDR3-FBGA96DIODE               DiodeDIP40-254           DIP40-254DOGESD_RClamp0524PA    FPC-24HDMI                miniHDMI-19P-SMDINDUCTOR_1JPO4                KEY-2PINLED                 NMOS_0              PMOS_0RES1R_P4                22R-1%SY8008B-AACSY8113BADC          TF08F-1113A1-XXXB-SNRmicrosd-1113a1T_POINT_RUSBXTAL-2P             XTAL-4P

    標(biāo)簽: hdmi ddr3

    上傳時(shí)間: 2022-01-09

    上傳用戶:bluedrops

  • DDR4標(biāo)準(zhǔn) JESD79_4

    1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout DESCRIPTION ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional DESCRIPTION ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command DESCRIPTION and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure DESCRIPTION .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34

    標(biāo)簽: DDR4

    上傳時(shí)間: 2022-01-09

    上傳用戶:

  • PCIE M.2 Pinout DESCRIPTION

    M.2的接口引腳定義,設(shè)計(jì)電路板的時(shí)候應(yīng)該用的著

    標(biāo)簽: pcie

    上傳時(shí)間: 2022-01-31

    上傳用戶:jason_vip1

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