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PCI（Peripheral Component Interconnect）局部總線是微型計(jì)算機(jī)中處理器、存儲(chǔ)器與外圍控制部件、擴(kuò)展卡之間的互連接口，由于其速度快、可靠性高、成本低、兼容性好等特點(diǎn)，在各種計(jì)算機(jī)總線標(biāo)準(zhǔn)占有重要地位，基于PCI標(biāo)準(zhǔn)的接口設(shè)計(jì)已經(jīng)成為相關(guān)項(xiàng)目開(kāi)發(fā)中的一個(gè)重要的選擇。 目前，現(xiàn)場(chǎng)可編程門(mén)陣列FPGA（Field Programmable Gates）得到了廣泛應(yīng)用。由于其具有規(guī)模大，開(kāi)發(fā)過(guò)程投資小，可反復(fù)編程，且支持軟硬件協(xié)同設(shè)計(jì)等特點(diǎn)，因此已逐步成為復(fù)雜數(shù)字硬件電路設(shè)計(jì)的首選。 PCI接口的開(kāi)發(fā)有多種方法，主要有兩種：一是使用專(zhuān)用接口芯片，二是使用可編程邏輯器件，如FPGA。本論文基于成本和實(shí)際需要的考慮，采用第二種方法進(jìn)行設(shè)計(jì)。 本論文采用自上而下（Top-To-Down）和模塊化的設(shè)計(jì)方法，使用FPGA和硬件描述語(yǔ)言（VHDL和Verilog HDL）設(shè)計(jì)了一個(gè)PCI接口核，并通過(guò)自行設(shè)計(jì)的試驗(yàn)板對(duì)其進(jìn)行驗(yàn)證。為使設(shè)計(jì)準(zhǔn)確可靠，在具體模塊的設(shè)計(jì)中廣泛采用流水線技術(shù)和狀態(tài)機(jī)的方法。 論文最終設(shè)計(jì)完成了一個(gè)33M32位的PCI主從接口，并把它作為以NIOSⅡ?yàn)楹诵牡腟OPC片內(nèi)外設(shè)，與通用計(jì)算機(jī)成功進(jìn)行了通訊。 論文對(duì)PCI接口進(jìn)行了功能仿真，仿真結(jié)果和PCI協(xié)議的要求一致，表明本論文設(shè)計(jì)正確。把設(shè)計(jì)下載進(jìn)FPGA芯片EP2C8Q208C7之后，論文給出了使用SIGNALTAPⅡ觀察到的信號(hào)實(shí)際波形，波形顯示PCI接口能夠滿(mǎn)足本設(shè)計(jì)中系統(tǒng)的需要。本文最后還給出試驗(yàn)板的具體設(shè)計(jì)步驟及驅(qū)動(dòng)程序的安裝。
標(biāo)簽： FPGA PCI 接口的設(shè)計(jì)
上傳時(shí)間： 2013-07-28
上傳用戶(hù)：372825274
英文描述： Synchronous Up/Down Decade Counters(single clock line) 中文描述： 同步向上/向下十年計(jì)數(shù)器（單時(shí)鐘線）
上傳時(shí)間： 2013-06-18
上傳用戶(hù)：haohaoxuexi
This unique guide to designing digital VLSI circuits takes a top-Down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.
標(biāo)簽： Integrated Digital Circuit Design
上傳時(shí)間： 2013-11-04
上傳用戶(hù)：life840315
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the device) with a conversion time Down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
上傳時(shí)間： 2014-12-23
上傳用戶(hù)：eastimage
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “Down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶(hù)：busterman
LED Dimmingcontrol
標(biāo)簽： Step-Down Dimming Driver Using
上傳時(shí)間： 2014-01-26
上傳用戶(hù)：watch100
1.2MHz 2A Synchronous Step-Down converter
上傳時(shí)間： 2013-11-01
上傳用戶(hù)：qingzhuhu
Abstract: Some types of loads require more current during startup than when running. Other loads can be limited to a lower-powercurrent during startup but require a higher operating current. This article describes an application circuit that automatically adjusts apower circuit’s overcurrent protection level up or Down after startup is complete.
標(biāo)簽： FET 保護(hù) 集成 電源開(kāi)關(guān)
上傳時(shí)間： 2013-10-23
上傳用戶(hù)：swaylong
The core voltages for FPGAs are moving lower as a resultof advances in the fabrication process. The newest FPGAfamily from Altera, the Stratix® II, now requires a corevoltage of 1.2V and the Stratix, Stratix GX, HardCopy®Stratix and CycloneTM families require a core voltage of1.5V. This article discusses how to power the core and I/Oof low voltage FPGAs using the latest step-Down switchmode controllers from Linear Technology Corporation.
標(biāo)簽： FPGA 低電壓 高性能開(kāi)關(guān) 電源解決方案
上傳時(shí)間： 2013-10-08
上傳用戶(hù)：wangfei22
The LTC®3414 offers a compact and efficient voltage regulatorsolution for point of load conversion in electronicsystems that require low output voltages (Down to 0.8V)from a 2.5V to 5V power bus. Internal power MOSFETswitches, with only 67mW on-resistance, allow theLTC3414 to deliver up to 4A of output current with efficiencyas high as 94%. The LTC3414 saves space by operatingwith switching frequencies as high as 4MHz, enabling theuse of tiny inductors and capacitors.
標(biāo)簽： 同步穩(wěn)壓器 元件 驅(qū)動(dòng) 負(fù)載
上傳時(shí)間： 2014-01-03
上傳用戶(hù)：dongbaobao
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