Dual Port RAM Asynchronous Read/Write 經(jīng)過(guò)modelsim仿真
標(biāo)簽： Asynchronous modelsim Write Dual
上傳時(shí)間： 2016-02-12
上傳用戶：xauthu
Top Level Dual Port Ram Core Project, VHDL code
標(biāo)簽： Project Level Dual Core
上傳時(shí)間： 2017-04-06
上傳用戶：ruixue198909
用SmartGen 生成一個(gè)2k*8 Dual Port RAM，并通過(guò)串口發(fā)送數(shù)據(jù)初始化RAM。然后通過(guò)串口返回到上位機(jī)的串口調(diào)試程序顯示。
標(biāo)簽： SmartGen Dual Port RAM
上傳時(shí)間： 2017-05-28
上傳用戶：z1191176801
is a test of a verilog implementation to do a oscilloscope with Dual-Port RAM
標(biāo)簽： implementation oscilloscope Dual-Port verilog
上傳時(shí)間： 2014-01-03
上傳用戶：15736969615
This application note describes how the existing Dual-Port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時(shí)間： 2013-11-08
上傳用戶：lou45566
使用Nios II緊耦合存儲(chǔ)器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時(shí)間： 2013-10-13
上傳用戶：黃婷婷思密達(dá)
This application note describes how the existing Dual-Port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時(shí)間： 2014-01-24
上傳用戶：15527161163
FIFO電路(first in，first out)，內(nèi)部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次讀出已經(jīng)寫(xiě)入的數(shù)據(jù)。因?yàn)椴淮嬖贏ddress輸入，所以請(qǐng)自行設(shè)計(jì)內(nèi)藏的讀寫(xiě)指針。由FIFO電路輸出的EF信號(hào)(表示RAM內(nèi)部的數(shù)據(jù)為空)和FF信號(hào)(表示RAM內(nèi)部的數(shù)據(jù)為滿)來(lái)表示RAM內(nèi)部的狀態(tài)，并且控制FIFO的輸入信號(hào)WEN(寫(xiě)使能)和REN(讀使能)。以及為了更好得控制FIFO電路，AEF(表示RAM內(nèi)部的數(shù)據(jù)即將空)信號(hào)也同時(shí)輸出。
上傳時(shí)間： 2016-02-06
上傳用戶：zhoujunzhen
CH341系列編程器芯片usb轉(zhuǎn)串口Altium Designer AD原理圖庫(kù)元件庫(kù)CSV text has been written to file : 1.9 - CH341系列編程器芯片.csvLibrary Component Count : 56Name Description----------------------------------------------------------------------------------------------------CH311Q PC debug port monitorCH331T Mini USB Disk ControllerCH340G CH340H USB to TTL Serial / UART, USB to IrDACH340T USB to TTL Serial / UART, USB to IrDACH340R USB to IrDA, USB to RS232 SerialCH340S_P USB to Print Port / ParallelCH340S_S USB to TTL Serial / UART, pin compatible with CH341CH341A_S USB to TTL Serial / UART / I2C/IICCH341S_P USB to Print Port / ParallelCH341A_P USB to Print Port / ParallelCH341S_S USB to TTL Serial / UARTCH341S_X USB to EPP Parallel / SPI / I2C/IICCH341A_X USB to EPP Parallel / SPI / I2C/IICCH341T USB to TTL Serial / UART / I2C/IICCH345T USB to MidiCH352L_M PCI to 8255 mode 2 Parallel for MCU and 16C550 UART / IrDACH352L_P PCI to Print Port / Parallel and 16C550 UART / IrDACH352L_S PCI to Dual 16C550 UART, TTL Serial*2 / IrDA*1CH362L PCI Device / Slave only for RAM / Expansion ROMCH364F Member of CH364 chipsetsCH364P PCI Device / Slave Embedded Flash ROM, for Expansion ROMCH365P PCI Device / Slave, for I/O port or RAM / ROMCH372T USB Device / Slave for MCU, ParallelCH372A USB Device / Slave for MCU, ParallelCH372V USB Device / Slave for MCU, ParallelCH374S USB Host & Device / Slave for MCU, parallel / SPICH374T USB Host & Device / Slave for MCU, parallel / SPICH375S USB Host & Device / Slave for MCU, parallel / UART SerialCH375A USB Host & Device / Slave for MCU, parallel / UART SerialCH375V USB Host & Device / Slave for MCU, parallel / UART SerialCH411G FDC MFM encode and decodeCH421A Dual port bufferCH421S Dual port bufferCH423D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423D_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423G I2C/IIC I/O expander, 6 GPO + 5 GPIOCH432Q Dual 16C550 UART with IrDA, parallel / SPICH432T SPI Dual 16C550 UART with IrDACH450K 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450H 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH451L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451S 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451D 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452L_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452L_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452S_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452S_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH453S 16 Digits / 128 LEDs Drive, I2C/IICCH453D 16 Digits / 128 LEDs Drive, I2C/IICPCI 32Bit PCI Bus, simple / short cardPCI32 32Bit PCI BusUSB USB Port
標(biāo)簽： ch341 編程芯片 usb 串口 altium designer
上傳時(shí)間： 2022-03-13
上傳用戶：
AT91RM9200 BSP with dual ethernet port
標(biāo)簽： ethernet 9200 with dual
上傳時(shí)間： 2017-09-06
上傳用戶：cainaifa
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