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1 Noise EnhAnced binary hypothesis-testing in a new framework
標簽：
hypothesis-testing
EnhAnced
binary
Noise
上傳時間：
2016-06-02
上傳用戶：siguazgb
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摘要
本研究計劃之目的，在整合應用以ARM為基礎的嵌入式多媒體實時操作系統(tǒng)于H.264/MPEG-4多媒體上。由于H.264是一種因應實時系統(tǒng)(RTOS)所設計的可擴展性串流傳輸(scalability stream media communication)的編碼技術(shù)。H.264主要架構(gòu)于細細粒可擴展(Fine Granula Scalability,FGS)的壓縮編碼機制。細粒度可擴展壓縮編碼技術(shù)是最新MPEG-4串流式傳輸標準，能依頻寛的差異來調(diào)整傳輸?shù)姆绞健＜毩６葦U展縮編碼技術(shù)以編入可選擇性的增強層(EnhAnced layers)于碼中，來提高影像傳輸?shù)馁|(zhì)量。本計劃主要在于設計一種簡單有效的實時階層可擴展的影像傳輸系統(tǒng)。在增強層編碼及H.264的基本層(base layer)編碼上使用漸進的細粒度可擴展編碼(Progressive Fine Granularity Scalable,PFGS)能直接使用H.264的格式特色來實現(xiàn)FGS。同時加入了LB-LLF(Layer-Based Least-Laxity-Fir stscheduling algorithm)的排程算法，來增
進網(wǎng)路傳輸影像的質(zhì)量。由實驗結(jié)果顯示本系統(tǒng)在串流影像質(zhì)量PSNR值上確有較佳的效能。
標簽：
芯片系統(tǒng)
架構(gòu)
開發(fā)平臺
上傳時間：
2014-12-26
上傳用戶：mpquest
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介紹了一種基于C8051F020單片機的多路壓力測量儀。該測量儀選用電阻應變式壓力傳感器采集壓力信號，并經(jīng)放大電路處理后送入C8051F020單片機，再由C8051F020單片機內(nèi)部的A/D轉(zhuǎn)換器將采集到的壓力信號進行模數(shù)轉(zhuǎn)化，然后分別對數(shù)據(jù)進行存儲和顯示。該測量儀能測量6路壓力信號，并且各測量點都能單獨檢測和設置。由于采用了C8051F020單片機，簡化了硬件電路，增強了抗干擾能力，使得測量儀具有測量精度高，沖擊小等特點。
Abstract:
A measurement apparatus for multi-channel pressure based on single chip microcomputer is introduced.It can measure 6 channels signal of the pressure，and the pressure measure points can be detection and located individually.The pressure signal sampling is obtained by resistor stress-type pressure sensors，the digital signals of 6 channels are collected through amplifying and adjustment circuit of pressure signals and internal integrated A/D converter of MCU.Finally，and it realizes the function to store and display data separately.C8051F020 was used to made hardware circuit simple，and it also EnhAnced the anti-interference ability.It features high precision and little impact.
標簽：
C8051F020
單片機
多路
壓力
上傳時間：
2013-11-16
上傳用戶：yare
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The LPC1769/68/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as EnhAnced debug features and a higher level of support block integration.
標簽：
LPC
1769
1768
1767
上傳時間：
2014-02-20
上傳用戶：13215175592
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly EnhAnced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, EnhAnced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標簽：
Cortex-M
1850
LPC
內(nèi)核微控制器
上傳時間：
2014-12-31
上傳用戶：zhuoying119
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, EnhAnced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標簽：
4300
LPC
ARM
雙核微控制器
上傳時間：
2013-10-28
上傳用戶：15501536189
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly EnhAnced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-21
上傳用戶：wxqman
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TMS Component Pack Pro Over 200 productivity VCL components, including grids, planning, scheduling, calendars, advanced edit controls, web update, EnhAnced listbox, treeview, combos, CAB file handling, and so much more
標簽：
productivity
components
scheduling
Component
上傳時間：
2013-12-22
上傳用戶：caiiicc
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jboss 開發(fā)人員 手冊
JBoss: A Developer s Notebook also introduces the management console, the web services messaging features, EnhAnced monitoring capabilities, and shows you how to improve performance. At the end of each lab, you ll find a section called "What about..." that anticipates and answers likely follow-up questions, along with a section that points you to articles and other resources if you need more information.
標簽：
introduces
management
Developer
the
上傳時間：
2015-04-17
上傳用戶：dreamboy36
