SVC最新更新代碼，fix了較多bug，增加了一些特性,詳細可見壓縮包內說明文檔2008年7月9日發布
上傳時間： 2013-12-26
上傳用戶：hullow
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標簽： bus bidirectional primarily designed
上傳時間： 2013-12-11
上傳用戶：jeffery
There a t least five Request for Enhancement s (RFE) in the JavaSoft bug database related to Mouse Wheel support in Java. One of the RFE s BugID #4202656 has 281 votes from developers requesting Sun for a fix. Sun has finally agreed to support this feature in JDK 1.4 codenamed Merlin accroding to the BugID #4289845 in its bug database.
標簽： Enhancement JavaSoft database Request
上傳時間： 2016-11-07
上傳用戶：
In this book, you will learn about what drives the Linux development process. You will discover the wide variety of tools commonly used by Linux developers – compilers, debuggers, Software Configuration Management – and how those tools are used to build application software, tools, utilities and even the Linux kernel itself. You will learn about the unique components of a Linux system that really set it apart from other UNIX-like systems, and you will delve into the inner workings of the system in order to better understand your role as one of a budding new generation of Linux developers.
標簽： will development the discover
上傳時間： 2016-11-18
上傳用戶：rocketrevenge
function [U,V,num_it]=fcm(U0,X) ％ MATLAB (Version 4.1) Source Code (Routine fcm was written by Richard J. ％ Hathaway on June 21, 1994.) The fuzzification constant ％ m = 2, and the stopping criterion for successive partitions is epsilon =??????. ％*******Modified 9/15/04 to have epsilon = 0.00001 and fix univariate bug******** ％ Purpose:The function fcm attempts to find a useful clustering of the ％ objects represented by the object data in X using the initial partition in U0.
標簽： fcm function Version Routine
上傳時間： 2014-11-30
上傳用戶：二驅蚊器
GPS 接收程序 DEMO。 HsGpsDll Library 1.1 A GPS Control/Component for C/C++ HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS receiver via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable of calling DLL functions. HsGpsDll allows a user application to read from a GPS device the current GPS position fix, velocity over ground (speed in kilometers per hour), plus number of of sattelites in view, current altitude (against mean sea level) and UTC date and time
標簽： HsGpsDll GPS Component Control
上傳時間： 2014-07-17
上傳用戶：thuyenvinh
200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • Linux® , Microsoft® Windows® CE-enabled MMU • 100-MHz System Bus • MaverickCrunch™ Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey™ IDs • 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. • Integrated Peripheral Interfaces • 32-bit SDRAM Interface
標簽： 8226 Cache kbyte Instruction
上傳時間： 2017-04-08
上傳用戶：comua
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
標簽： increasingly description designing languages
上傳時間： 2014-01-08
上傳用戶：小草123
利用宏編譯將程序的調試部分與主體部分分隔開，即編譯開關DEBUG、MIDEBUG、 TRANSDEBUG、SEARCHDEBUG *fix bug: cvGeTransform()的內存泄漏問題(調整函數接口，使得內存損耗降為6M) *加入了保存配準結果的功能(包括保存配準圖像，配準數據RegisterLog.txt) *去掉save菜單，直接加到register選項中，且保存文件名自動隨機生成 ******圖像配準失敗的原因：主要是由于多模圖像的特征點自動選取時的誤差，對同模式圖像配準效果很好
上傳時間： 2017-06-04
上傳用戶：weixiao99
As I write this foreword, I am collaborating with four leading user interface (UI) component vendors on a presentation for the 2004 JavaOneSM conference. In our presentation, the vendors will show how they leverage JavaServerTM Faces technology in their products. While developing the presentation, I am learning some things about the work we’ve been doing on JavaServer Faces for the past three years. The vendors have their own set of concerns unique to adapting their product for JavaServer Faces, but they all voice one opinion loud and clear: they are very relieved to finally have a standard for web-based user interfaces.
標簽： collaborating component interface foreword
上傳時間： 2014-08-27
上傳用戶：時代電子小智
