本軟件是關于MAX338, MAX339的英文數據手冊：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時間： 2013-11-12
上傳用戶：18711024007
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時間： 2013-11-21
上傳用戶：不懂夜的黑
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時間： 2014-01-11
上傳用戶：a471778
WP369可擴展式處理平臺-各種嵌入式系統的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間： 2013-10-18
上傳用戶：cursor
數字與模擬電路設計技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導體組件所構成，雖然半導體組件高速、高頻化時會有EMI的困擾，不過為了充分發揮半導體組件應有的性能，電路板設計與封裝技術仍具有決定性的影響。 模擬與數字技術的融合由于IC與LSI半導體本身的高速化，同時為了使機器達到正常動作的目的，因此技術上的跨越競爭越來越激烈。雖然構成系統的電路未必有clock設計，但是毫無疑問的是系統的可靠度是建立在電子組件的選用、封裝技術、電路設計與成本，以及如何防止噪訊的產生與噪訊外漏等綜合考慮。機器小型化、高速化、多功能化使得低頻/高頻、大功率信號/小功率信號、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數字電路，經常出現在同一個高封裝密度電路板，設計者身處如此的環境必需面對前所未有的設計思維挑戰，例如高穩定性電路與吵雜(noisy)性電路為鄰時，如果未將噪訊入侵高穩定性電路的對策視為設計重點，事后反復的設計變更往往成為無解的夢魘。模擬電路與高速數字電路混合設計也是如此，假設微小模擬信號增幅后再將full scale 5V的模擬信號，利用10bit A/D轉換器轉換成數字信號，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結果造成10bit以上的A/D轉換器面臨無法順利運作的窘境。另一典型實例是使用示波器量測某數字電路基板兩點相隔10cm的ground電位，理論上ground電位應該是零，然而實際上卻可觀測到4.9mV數倍甚至數十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數字混合電路的grand所造成的話，要測得4.9 mV的信號根本是不可能的事情，也就是說為了使模擬與數字混合電路順利動作，必需在封裝與電路設計有相對的對策，尤其是數字電路switching時，ground vance noise不會入侵analogue ground的防護對策，同時還需充分檢討各電路產生的電流回路(route)與電流大小，依此結果排除各種可能的干擾因素。以上介紹的實例都是設計模擬與數字混合電路時經常遇到的瓶頸，如果是設計12bit以上A/D轉換器時，它的困難度會更加復雜。
上傳時間： 2014-02-12
上傳用戶：wenyuoo
本文將接續介紹電源與功率電路基板，以及數字電路基板導線設計。寬帶與高頻電路基板導線設計a.輸入阻抗1MHz，平滑性(flatness)50MHz 的OP增幅器電路基板圖26 是由FET 輸入的高速OP 增幅器OPA656 構成的高輸入阻抗OP 增幅電路，它的gain取決于R1、R2，本電路圖的電路定數為2 倍。此外為改善平滑性特別追加設置可以加大噪訊gain，抑制gain-頻率特性高頻領域時峰值的R3。圖26 高輸入阻抗的寬帶OP增幅電路圖27 是高輸入阻抗OP 增幅器的電路基板圖案。降低高速OP 增幅器反相輸入端子與接地之間的浮游容量非常重要，所以本電路的浮游容量設計目標低于0.5pF。如果上述部位附著大浮游容量的話，會成為高頻領域的頻率特性產生峰值的原因，嚴重時頻率甚至會因為feedback 阻抗與浮游容量，造成feedback 信號的位相延遲，最后導致頻率特性產生波動現象。此外高輸入阻抗OP 增幅器輸入部位的浮游容量也逐漸成為問題，圖27 的電路基板圖案的非反相輸入端子部位無full ground設計，如果有外部噪訊干擾之虞時，接地可設計成網格狀(mesh)。圖28 是根據圖26 制成的OP 增幅器Gain－頻率特性測試結果，由圖可知即使接近50MHz頻率特性非常平滑，-3dB cutoff頻率大約是133MHz。
標簽： PCB
上傳時間： 2013-11-09
上傳用戶：z754970244
這個軟件需要你的本機操作的。其他機器是算不出來的！ 就是說 一臺電腦只有一個注冊碼對應！ 這里有個辦法： MULTISIM2001安裝方法： 一：運行SETUP.EXE安裝。在安裝時，要重新啟動計算機一次。 二：啟動后在“開始>程序”中找到STARTUP項，運行后，繼續進行安裝，安裝過程中，第一次要求輸入“CODE"碼時， 輸入“PP-0411-48015-7464-32084"輸入后，會提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO." 按確定，又會出現一個“feature code”框，輸入“FC-6424-04180-0044-13881”后， 在彈出的對話框中選擇“取消”，一路確定即可完成安裝。 三：1.運行VERILOG目錄內的SETUP安裝 2.運行FPGA目錄內的SETUP安裝 3.將CRACK目錄內的LICMGR.DLL拷貝到WINDOWS系統的SYSTEM 目錄內 4.并將VERILOG安裝目錄內的同名文件刪除 5.將SILOS.LIC文件拷到VERILOG安裝目錄內覆蓋原文件，并作如下編輯： 6.將“COMPUTER_NAME”替換為你的機器名 7.將“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替換為你的 實際安裝路徑。如此你便可以使用VERILOG了。 四：安裝之后，運行MULTISIM2001,會要求輸入“RELEASE CODE",不用著急， 記下“SERIAL NUMBER"和“SIGNATURE NUMBER", 使用CRACK目錄內的注冊器“MULTISIM KEYGEN.EXE" 將剛才記下的兩個號碼分別填入后， 即可得到"RELEASE CODE", 以后就可以正常使用了。 五：接下來運行 database update目錄中的幾個文件， 進行數據庫合并即可。祝你成功！！ 六：啟動MULTISIM2001時候的注冊碼 1： PP-0411-48015-7464-32084 2： 37506-86380 3:的三個空格 1975 2711 4842 里面包含了：Multisim2001漢化破解版、Multisim.V10.0.1.漢化破解版圖解 解壓密碼：www.pp51.com
上傳時間： 2013-11-16
上傳用戶：天空說我在
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上傳時間： 2013-11-21
上傳用戶：tian126vip
SL811開發資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
上傳時間： 2013-12-22
上傳用戶：a82531317
