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Field-Cooled

  • 基于塑料光纖的高壓隔離通信接口設(shè)計(jì)

     通過比較各種隔離數(shù)字通信的特點(diǎn)和應(yīng)用范圍,指出塑料光纖在隔離數(shù)字通信中的優(yōu)勢(shì)。使用已經(jīng)標(biāo)準(zhǔn)化的TOSLINK接口,有利于節(jié)省硬件開發(fā)成本和簡(jiǎn)化設(shè)計(jì)難度。給出了塑料光纖的硬件驅(qū)動(dòng)電路,說明設(shè)計(jì)過程中的注意事項(xiàng),對(duì)光收發(fā)模塊的電壓特性和頻率特性進(jìn)行全面試驗(yàn),并給出SPI口使用塑料光纖隔離通信的典型應(yīng)用電路圖。試驗(yàn)結(jié)果表明,該設(shè)計(jì)可為電力現(xiàn)場(chǎng)、電力電子及儀器儀表的設(shè)計(jì)提供參考。 Abstract:  y comparing characteristics and applications area of various isolated digital communications, this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface, it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module, explains the noticed details in design process, gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally,it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field, power electronics and instrumentation design.

    標(biāo)簽: 塑料光纖 高壓隔離 通信 接口設(shè)計(jì)

    上傳時(shí)間: 2014-01-10

    上傳用戶:gundan

  • 101-200晶體管電路集

    This is the second half of our Transistor Circuits e-book. It contains a further 100 circuits, with many of them containing one or more Integrated Circuits (ICs).It's amazing what you can do with transistors but when Integrated Circuits came along, the whole field of electronics exploded.

    標(biāo)簽: 101 200 晶體管 電路

    上傳時(shí)間: 2013-11-08

    上傳用戶:603100257

  • MAXQUSBJTAGOW評(píng)估板軟件

    MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    標(biāo)簽: MAXQUSBJTAGOW 評(píng)估板 軟件

    上傳時(shí)間: 2013-10-24

    上傳用戶:teddysha

  • MAXQUSBJTAGOW評(píng)估板軟件

    MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD

    標(biāo)簽: MAXQUSBJTAGOW 評(píng)估板 軟件

    上傳時(shí)間: 2013-11-23

    上傳用戶:truth12

  • Create a 1-Wire Master with Xilinx PicoBlaze

    Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.

    標(biāo)簽: PicoBlaze Create Master Xilinx

    上傳時(shí)間: 2013-11-12

    上傳用戶:大三三

  • Analog Solutions for Altera FPGAs

    Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)

    標(biāo)簽: Solutions Analog Altera FPGAs

    上傳時(shí)間: 2013-10-27

    上傳用戶:fredguo

  • Analog Solutions for Xilinx FPGAs

    Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables

    標(biāo)簽: Solutions Analog Xilinx FPGAs

    上傳時(shí)間: 2013-11-07

    上傳用戶:suicone

  • XAPP098 - Spartan FPGA低成本、高效率串行配置

    This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.

    標(biāo)簽: Spartan XAPP FPGA 098

    上傳時(shí)間: 2013-11-01

    上傳用戶:wojiaohs

  • CPLD和FPGA設(shè)計(jì)介紹

    Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

    標(biāo)簽: CPLD FPGA

    上傳時(shí)間: 2013-10-22

    上傳用戶:lmq0059

  • allegro cx manual教程

    We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi  eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi  eld.  

    標(biāo)簽: allegro manual cx 教程

    上傳時(shí)間: 2015-01-02

    上傳用戶:zhangyi99104144

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