This paper presents several low-latency mixed-timing
FIFO (First-in–first-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either synchronous or asynchronous. The designs are then
adapted to work between systems with very long interconnect
delays, by migrating a single-clock solution by Carloni et al.
(1999, 2000, and 2001) (for “l(fā)atency-insensitive” protocols) to
mixed-timing domains. The new designs can be made arbitrarily
robust with regard to metastability and interface operating speeds.
Initial simulations for both latency and throughput are promising.
FIFO電路(first in，first out)，內(nèi)部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次讀出已經(jīng)寫入的數(shù)據(jù)。因為不存在Address輸入，所以請自行設(shè)計內(nèi)藏的讀寫指針。由FIFO電路輸出的EF信號(表示RAM內(nèi)部的數(shù)據(jù)為空)和FF信號(表示RAM內(nèi)部的數(shù)據(jù)為滿)來表示RAM內(nèi)部的狀態(tài)，并且控制FIFO的輸入信號WEN(寫使能)和REN(讀使能)。以及為了更好得控制FIFO電路，AEF(表示RAM內(nèi)部的數(shù)據(jù)即將空)信號也同時輸出。
c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.
3D FDTD 計算程序
ToyFDTD1 is a stripped-down, minimalist, 3-dimensional FDTD code that is published under the GNU General Public License. It is the first in the ToyFDTD series of codes, and it illustrates in heavily commented C and Fortran the basic tasks in implementing a simple 3D FDTD simulation.
