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The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽：
lpc
datasheet
2292
2294
上傳時(shí)間：
2014-12-30
上傳用戶：aysyzxzm
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽：
Virtex
FPGA
PCB
設(shè)計(jì)手冊(cè)
上傳時(shí)間：
2013-11-11
上傳用戶：zwei41
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This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
標(biāo)簽：
XAPP
806
DDR
DCM
上傳時(shí)間：
2014-11-26
上傳用戶：erkuizhang
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you
solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,
distribute, republish, download, display, post, or transmit the Documentation in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.
Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx
assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections
or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be
provided to you in connection with the Information.
標(biāo)簽：
CPLD
上傳時(shí)間：
2014-12-05
上傳用戶：qazxsw
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摘要: 串行傳輸技術(shù)具有更高的傳輸速率和更低的設(shè)計(jì)成本, 已成為業(yè)界首選, 被廣泛應(yīng)用于高速通信領(lǐng)域。提出了一種新的高速串行傳輸接口的設(shè)計(jì)方案, 改進(jìn)了Aurora 協(xié)議數(shù)據(jù)幀格式定義的弊端, 并采用高速串行收發(fā)器Rocket I/O, 實(shí)現(xiàn)數(shù)據(jù)率為2.5 Gbps的高速串行傳輸。關(guān)鍵詞: 高速串行傳輸; Rocket I/O; Aurora 協(xié)議
為促使FPGA 芯片與串行傳輸技術(shù)更好地結(jié)合以滿足市場(chǎng)需求, Xilinx 公司適時(shí)推出了內(nèi)嵌高速串行收發(fā)器RocketI/O 的Virtex II Pro 系列FPGA 和可升級(jí)的小型鏈路層協(xié)議———Aurora 協(xié)議。Rocket I/O支持從622 Mbps 至3.125 Gbps的全雙工傳輸速率, 還具有8 B/10 B 編解碼、時(shí)鐘生成及恢復(fù)等功能, 可以理想地適用于芯片之間或背板的高速串行數(shù)據(jù)傳輸。Aurora 協(xié)議是為專有上層協(xié)議或行業(yè)標(biāo)準(zhǔn)的上層協(xié)議提供透明接口的第一款串行互連協(xié)議, 可用于高速線性通路之間的點(diǎn)到點(diǎn)串行數(shù)據(jù)傳輸, 同時(shí)其可擴(kuò)展的帶寬, 為系統(tǒng)設(shè)計(jì)人員提供了所需要的靈活性[4]。但該協(xié)議幀格式的定義存在弊端,會(huì)導(dǎo)致系統(tǒng)資源的浪費(fèi)。本文提出的設(shè)計(jì)方案可以改進(jìn)Aurora 協(xié)議的固有缺陷,提高系統(tǒng)性能, 實(shí)現(xiàn)數(shù)據(jù)率為2.5 Gbps 的高速串行傳輸, 具有良好的可行性和廣闊的應(yīng)用前景。
標(biāo)簽：
Rocket
2.5
高速串行
收發(fā)器
上傳時(shí)間：
2013-10-13
上傳用戶：lml1234lml
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USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
標(biāo)簽：
xilinx
VHDL
USB
us
上傳時(shí)間：
2013-10-29
上傳用戶：zhouchang199
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題目：利用條件運(yùn)算符的嵌套來完成此題：學(xué)習(xí)成績>=90分的同學(xué)用A表示，60-89分之間的用B表示，60分以下的用C表示。 1.程序分析：(a>b)?a:b這是條件運(yùn)算符的基本例子。
標(biāo)簽：
gt
90
運(yùn)算符
嵌套
上傳時(shí)間：
2015-01-08
上傳用戶：lifangyuan12
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用Java寫的報(bào)表.功能如下: 0.內(nèi)建網(wǎng)絡(luò)打印,網(wǎng)絡(luò)預(yù)覽功能！ 1.文件操作。包括url 指定的文件。 2.全功能打印支持。包括打印預(yù)覽。 3.Undo 和 redo。 4.合并單元格。 5.Cell selection using the mouse or keyboards（快捷鍵支持）。 6.單元格高寬調(diào)整 。 7.豐富的前景刷支持，前景可以是單色，雙色漸變，JPG,PNG,GIF圖形 。 8.背景刷支持，前景可以是單色，雙色漸變，JPG,PNG,GIF圖形 。 9.每個(gè)單元格支持空心字體，各其他一般字體。 10.每個(gè)單元格可設(shè)置為只讀。 11.每個(gè)單元格上下左右可分別高設(shè)置邊框，邊框線的寬度，顏色可調(diào)。 12.拖放操作。可在一個(gè)應(yīng)用中的不同單元格拖放，也可在兩個(gè)應(yīng)用的之間進(jìn)行拖放。支持剪切和COPY兩種方式。 13.剪貼板功能。支持文本方式和全格式兩種方式。剪貼也允許在兩個(gè)應(yīng)用之間進(jìn)行。可以從EXCELL單元格中復(fù)制到本應(yīng)用中。 14.單元格線，滾動(dòng)條，行頭，列頭顯示可選. 15.支持公式定義,公式定義采用？作標(biāo)記，如?sum(A1:B1)。 16.數(shù)字格式可自由定義，如 12345678, 可自動(dòng)化為 12,345,678.00 。 17.豐富的頁腳頁眉屬性。具有以上3，4，5，6?，8，9，10，11，12，13，15,16，17各項(xiàng)功能。
標(biāo)簽：
Java
Undo
redo
Cel
上傳時(shí)間：
2015-03-15
上傳用戶：熊少鋒
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基于matlab的mp3的讀寫函數(shù)Mp3 toolbox for Matlab. Alfredo Fernandez Franco Aalborg University Departament of Acoustics M.Sc. Student aberserk@yahoo.com Includes 2 functions to write and read MP3 files. It works like the commands WAVWRITE and WAVREAD. 1.- Just unpack in the toolbox folder under the MATLAB directory. 2.- Set the MATLAB search path to include that folder. This version was made in MATLAB for WINDOWS only. I ll probably will make the UNIX version later. 01-11-2004.
標(biāo)簽：
Departament
University
Fernandez
Alfredo
上傳時(shí)間：
2014-12-02
上傳用戶：開懷常笑
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RSA算法 :首先, 找出三個(gè)數(shù), p, q, r, 其中 p, q 是兩個(gè)相異的質(zhì)數(shù), r 是與 (p-1)(q-1) 互質(zhì)的數(shù)...... p, q, r 這三個(gè)數(shù)便是 person_key，接著, 找出 m, 使得 r^m == 1 mod (p-1)(q-1)..... 這個(gè) m 一定存在, 因?yàn)?r 與 (p-1)(q-1) 互質(zhì), 用輾轉(zhuǎn)相除法就可以得到了..... 再來, 計(jì)算 n = pq....... m, n 這兩個(gè)數(shù)便是 public_key ，編碼過程是, 若資料為 a, 將其看成是一個(gè)大整數(shù), 假設(shè) a < n.... 如果 a >= n 的話, 就將 a 表成 s 進(jìn)位 (s
標(biāo)簽：
person_key
RSA
算法
上傳時(shí)間：
2013-12-14
上傳用戶：zhuyibin
