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GENERATEd

  • pppdump

    pppdump - print out the contents of a record file GENERATEd by  pppd in readable form

    標(biāo)簽: ppp ppp解析

    上傳時(shí)間: 2016-03-26

    上傳用戶:guoshuai1996

  • 研旭DSP2812Basic板原理圖

    研旭DSP2812Basic板原理圖 GENERATEd by Foxit PDF Creator 

    標(biāo)簽: Basic 2812 DSP 原理圖

    上傳時(shí)間: 2019-03-31

    上傳用戶:cf200300

  • Optical Wireless Communication Systems

    Optical wireless communication is an emerging and dynamic research and development area that has GENERATEd a vast number of interesting solutions to very complicated communication challenges. For example, high data rate, high capacity and minimum interference links for short-range communication for inter-building communication, computer-to-computer communication, or sensor networks. At the opposite extreme is a long-range link in the order of millions of kilometers in the new mission to Mars and other solar system planets.

    標(biāo)簽: Communication Wireless Optical Systems

    上傳時(shí)間: 2020-05-31

    上傳用戶:shancjb

  • Chemical mechanical polishing

    The planarization technology of Chemical-Mechanical-Polishing (CMP), used for the manufacturing of multi- level metal interconnects for high-density Integrated Circuits (IC), is also readily adaptable as an enabling technology in MicroElectroMechanical Systems (MEMS) fabrication, particularly polysilicon surface micromachining. CMP not only eases the design and manufacturability of MEMS devices by eliminating several photolithographic and film issues GENERATEd by severe topography, but also enables far greater flexibility with process complexity and associated designs. T

    標(biāo)簽: mechanical polishing Chemical

    上傳時(shí)間: 2020-06-06

    上傳用戶:shancjb

  • 電子書-RTL Design Style Guide for Verilog HDL540頁

    電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is GENERATEd from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.

    標(biāo)簽: RTL verilog hdl

    上傳時(shí)間: 2022-03-21

    上傳用戶:canderile

  • 天龍功放AVR1506的用戶手冊(cè)(英文版)

    如果在調(diào)諧器或電視機(jī)附近使用本機(jī)或任何其他使用微處理器的電子設(shè)備,則可能會(huì)產(chǎn)生圖像的噪聲或干擾。如果發(fā)生這種情況,請(qǐng)采取以下步驟將本機(jī)安裝在盡可能遠(yuǎn)離調(diào)諧器或T的地方。遠(yuǎn)離調(diào)諧器或T,遠(yuǎn)離本機(jī)的電源線和輸入/輸出連接電纜。尤其在使用室內(nèi)天線或300歐姆饋線。我們建議使用室外天線和75 Q / ohm同軸電纜Noise or disturbance of the picture may be GENERATEd if this unit or any other electronic equipment using microprocessors is used near a tuner or TV If this happens, take the following stepsInstall this unit as far away as possible from the tuner or T Run the antenna wires from the tuner or T away from this unit ' s power supply cord and input/output connection cables. Noise or disturbance tends to occur particularly when using indoor antennas or300 ohm feeder wires. We recommend using outdoor antennas and 75 Q/ohm coaxial cables

    標(biāo)簽: 功放

    上傳時(shí)間: 2022-04-22

    上傳用戶:

  • 基于DSP28335+I(xiàn)R2110芯片的移相全橋驅(qū)動(dòng)電路設(shè)計(jì)

    為解決移相全橋電路驅(qū)動(dòng)及相角控制問題,設(shè)計(jì)了一種數(shù)字控制的移相全橋驅(qū)動(dòng)電路.以TPL521為光耦隔離、IR2110為柵極驅(qū)動(dòng)芯片.由DSP產(chǎn)生PWM信號(hào),經(jīng)過光耦隔離和邏輯電路后送至IR2110進(jìn)行相角控制.文章對(duì)IR2110驅(qū)動(dòng)電路原理進(jìn)行分析及參數(shù)進(jìn)行設(shè)計(jì),對(duì)TMS320F28335進(jìn)行設(shè)置并給出部分代碼.實(shí)驗(yàn)結(jié)果表明:通過TMS320F28335可產(chǎn)生的不同相角的PWM波形,滿足了移相全橋?qū)Σ煌嘟强刂频囊?In order to solve the problem of phase-shifted full-bridge circuit driving and phase angle control,a digitally controlled phaseshifted full-bridge driving circuit was designed. TPL521 optocoupler isolation,IR2110 gate driver chip. PWM signals are GENERATEd by the DSP and sent to the IR2110 for phase angle control after optocoupler isolation and logic circuits. This text carries on the analysis to the principle of IR2110 drive circuit and parameter design,set up and give out some code to TMS320F28335. The experimental results show that the PWM waveforms with different phase angles GENERATEd by TMS320F28335 can meet the requirements of phase-shifted full-bridge control for different phase angles.

    標(biāo)簽: dsp28335 ir2110 芯片

    上傳時(shí)間: 2022-05-03

    上傳用戶:zhanglei193

  • VIP專區(qū)-嵌入式/單片機(jī)編程源碼精選合集系列(135)

    VIP專區(qū)-嵌入式/單片機(jī)編程源碼精選合集系列(135)資源包含以下內(nèi)容:1. AT89C52紅外接收c源碼 已經(jīng)過調(diào)試 下載即可使用.2. 步進(jìn)電機(jī)驅(qū)動(dòng)控制技術(shù)及其應(yīng)用設(shè)計(jì)研究 一編論文.3. Nucleus PLUS source code anasisy. An open source OS which is widely used in embedded development dom.4. 數(shù)字系統(tǒng)CAD 開發(fā)平臺(tái)實(shí)驗(yàn)部分共有6 個(gè)實(shí)驗(yàn).5. 12位ads7816的兩種讀取方式:SPI方式和手動(dòng)方式.6. 可用于嵌入式編程學(xué)習(xí).7. ADE7755應(yīng)用于單相CPU卡表的硬件設(shè)計(jì)原理圖.8. 電能表的結(jié)構(gòu)原理介紹和工作原理介紹.9. 這是一個(gè)關(guān)于C++編程規(guī)范的資料.10. C/C++bianchengguifan.11. 賽車程序:先對(duì)賽道和賽車建立模型.12. This document teach how you interface the microcontroller to the devices using i2c , spi and serial.13. 我收集的一些I2C的技術(shù)文檔和在linux環(huán)境的應(yīng)用分析等.14. 模糊PID在電阻爐溫度控制系統(tǒng)中的應(yīng)用。提出了FUZZY-PID控制器.15. 在網(wǎng)站上找到的一個(gè)比較不錯(cuò)的字符疊加程序.16. 包的運(yùn)用.17. 嵌入式高速數(shù)據(jù)采集器的研制.18. 嵌入式C_C++語言精華文章集錦.19. Visual C++網(wǎng)絡(luò)通信協(xié)議分析與應(yīng)用實(shí)現(xiàn)代碼.20. 嵌入式C編程語言入門與深入.21. 周立功的PCI51XX CAN卡在VC6.0下的開發(fā)示例.22. 飛思卡爾S12系Serial_Peripheral_Interphase_(SPI)應(yīng)用范例.23. 飛思卡爾S12系列Inter-IC_Bus__(IIC)應(yīng)用范例.24. 開機(jī)時(shí).25. 簡(jiǎn)單的程序.26. U2270B組成的讀卡頭原理圖!典型應(yīng)用電路.27. lpc214x的開發(fā)平臺(tái)下載軟件 使用lpc214x的開發(fā).28. ZIGBEE1015無線傳感器統(tǒng)會(huì)自動(dòng)刪除debug和release目錄.29. Introduction: 1. Macro1: AddFailureModeCol is used to the test report GENERATEd from GNPO Rpt Tools.30. 適合用于嵌入式的zc301攝像頭驅(qū)動(dòng)。解壓縮之后放在/driver/media/video/zc0301目錄下.31. 開源嵌入式圖形軟件FLTK使用 視頻教程.32. jz4740 nand boot source code. jz4740 nand 引導(dǎo)代碼.33. 用C++寫的一個(gè)模擬ATM自動(dòng)取款機(jī)的程序.我這個(gè)程序不同于網(wǎng)上現(xiàn)有的那個(gè)不能記錄用戶填寫信息的..34. 該電子日歷可顯示年、月、日、星期、時(shí)、分的時(shí)間信息。 整個(gè)系統(tǒng)采用AT89C52作為中央處理芯片.35. 讓你了解AODV在OPNET下怎么運(yùn)用.36. 基于GPS定位的嵌入式汽車監(jiān)控器設(shè)計(jì).37. 使用手冊(cè).38. Zigbee培訓(xùn)資料.39. EASYARM2210的原理圖 設(shè)計(jì)ARM硬件的重要參考.40. 嵌入式平臺(tái)的開發(fā)全過程 非常易懂 嵌?朧狡教ǖ目⑷?非常易懂.

    標(biāo)簽: 夜視

    上傳時(shí)間: 2013-05-25

    上傳用戶:eeworm

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