The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上傳時間： 2013-11-13
上傳用戶：fredguo
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
上傳時間： 2014-01-18
上傳用戶：bs2005
The outputs of the PCA9518 are immediately available as soon as there is a voltage present on thesupply >~1V and behave as described above. The power-on reset of the PCA9518A keeps the outputsturned off during power-up and maintains the high impedance of the outputs throughout the power-upcycle. There is an additional built-in delay after power-up that allows the analog circuits to stabilize beforethe part is activated.
標簽： Replacement 9518 NXP PCA
上傳時間： 2013-10-26
上傳用戶：13817753084
Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
上傳時間： 2013-10-14
上傳用戶：cxl274287265
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging sensitive circuitry.
上傳時間： 2013-10-24
上傳用戶：hbsunhui
基于單片機的除塵控制器的設計:介紹通用控制儀的硬件組成和軟件設計,闡述了系統的性能指標和功能特點。該產品功能完善,可靠性高,具有很好的應用前景。關鍵詞: 除塵器;通用控制儀;單片機;系統設計 Abstract: The hardware structure and the software design are introduced in this paper, and the performance index and the features of the system are expounded. It has comp rehensive functions, high reliability and good app lication.Key words: dust catcher; universal controller; microcontroller; system design
上傳時間： 2013-11-16
上傳用戶：ming52900
摘要：本水位監測報警器使用5V低壓直流電源（也可以用3節5號電池代替）就可以對5~15厘米的水位進行監測，用LED顯示和數碼管顯示水位，并可以對不再此范圍內的水位發出報警。主要采用CD4066、74LS86、74LS32、CD4511芯片，再加上數碼管、蜂鳴器、發光二極管、電阻這些器件組成一個簡單而靈敏的監測報警電路，操作簡單，接通電源即可工作。因為大部分電路采用數字電路，所以本水位監測報警器還具有耗能低、準確性高的特點。關鍵字：譯碼電路 報警電路 監測電路 Abstract: The water level alarm monitoring the use of 5 V low-voltage DC power (can also use three batteries replaced on the 5th) will be able to 5 to 15 centimeters of water level monitoring, with LED display and digital display of water level, and this can no longer Within the scope of a water level alarm. Mainly CD4066, 74LS86, 74LS32, CD4511 chips, coupled with digital control, buzzer, light-emitting diode, the resistance of these devices composed of a simple and sensitive monitoring alarm circuits. Because the majority of circuits using digital circuitry, so the water level monitored alarm system also has low energy consumption, high accuracy of the characteristics. Keyword: Decoding circuit alarm circuit monitoring circuit
上傳時間： 2013-11-05
上傳用戶：王慶才
基于單片機控制的二氧化碳濃度測試計:基于CDM4161二氧化碳氣體濃度測試模塊以及ATtiny26單片機,提出了一種二氧化碳濃度測試計的設計方案。該方案具有硬件電路簡單、成本低、可靠性高、測量準確等優點，具有較高的實用價值。 Abstract: Abstract：A desigh scheme of CO2 concentration meter based on CDM4161carbon dioxide concentration test module and ATtiny26micro-controller is presented in this paper.The design scheme features simple hardware circuit,low-cost,high reli-ability，accurate measurement and it has a high practical value.
上傳時間： 2013-11-14
上傳用戶：zjwangyichao
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上傳時間： 2013-10-08
上傳用戶：18711024007
The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps
上傳時間： 2013-11-05
上傳用戶：uuuuuuu
