In the rectangle packing problem, encoding schemes to represent the placements of rectangles are the key factors determining the efficiency of algorithms. SEQP AIR is one of the most sophisticated encoding sheme, which has been considered to have a small solution space
標簽： placements rectangles the rectangle
上傳時間： 2013-12-24
上傳用戶：hphh
The objective is to set up SPI communication between VTI Technologies digital pressure sensor component and an MCU of an application device ATMEGA16L. In this code example: ?The MCU is configured ?SCP1000-D01 is initialized and configured ?The high resolution measurement mode is activated ?Temperature and pressure information is read always when the DRDY pin is in high state Please refer to the document "SCP1000 Product Family Specification 8260800" for further information on SCP1000 register addressing and SPI communication. This document applies to the SCP1000-D01.
標簽： communication Technologies objective pressure
上傳時間： 2017-06-17
上傳用戶：youmo81
基于LPC2478硬件平臺的IAP和遠程WEB應用。 系統共分為三個部分，BOOT區，LOW區和HIGH區?？赏ㄟ^WEB實現對芯片的遠程IAP在線升級.
上傳時間： 2017-06-28
上傳用戶：huannan88
Short description: A MAX-MIN Ant System (MMAS) implemented in the Hyper-Cube Framework for the application to Unconstrained Binary Quadratic Programming (UBQP). Aim of the software: Educational (not high-performance) it shows how to implement a MMAS in the Hyper-Cube Framework.
標簽： description implemented Hyper-Cube Framework
上傳時間： 2014-11-26
上傳用戶：蠢蠢66
The MINI2440 is an effecient ARM9 development board with a comprehensive price, it characterizes simple method and high performance-price ratio. Based on the Samsung S3C2440 microprocessor, it embodies professional stable CPU core power source chip and reset chip to ensure the stability of the system operation. The PCB on the MINI2440 board is designed to be 4-layers board, adopting the ENIG technology and professional equal-length wiring to ensure the completeness of the signals of the key signal wires and manufactured and released under stringent quality control plans. With the help of this detailed manual, users are supposed to become proficient in the development process of embedded Linux and WinCE operating system, they are supposed to get the foundation, so long as they have obtained the basic and necessary knowledge about the C language, in two weeks.
標簽： comprehensive characterizes development effecient
上傳時間： 2013-12-18
上傳用戶：csgcd001
-- ------------------------------------------------------------------------------------ -- DESCRIPTION : Demultiplexer -- Width: 8 -- Number of terminals: 4 -- Output enable active: HIGH -- Output active : HIGH -- Download from : http://www.pld.com.cn ------------------------------------------------------------------------------------
標簽： DESCRIP
上傳時間： 2013-12-27
上傳用戶：wangzhen1990
The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been researched. The function module, state machine of digital DC/DC controller and high resolution DPWM with Sigma- Delta dither has been introduced. They are verified by experiments on a 20 W, 300 KHz non-isolated synchronous buck converters.
標簽： Converters controller optimized Digital
上傳時間： 2013-12-31
上傳用戶：tzl1975
RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
標簽： using fundamental the RS_latch
上傳時間： 2017-07-30
上傳用戶：努力努力再努力
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web.
標簽： implementation describes mastering protocol
上傳時間： 2014-06-16
上傳用戶：teddysha
NEA1803 51單片機與12864 由串口中斷收取數據 顯示經度緯度 高度 速度 時間 使用衛星數-GPS development NEA1803 51 SCM and 12864 collected by the serial interrupt data show a high degree of longitude latitude speed time-use satellite
標簽： 12864 1803 development NEA
上傳時間： 2017-08-22
上傳用戶：lepoke
