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Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分
Nios® II embedded processor cores can contain instruction and data caches. This
chapter discusses cache-related issues that you need to consider to guarantee that
your program executes correctly on the Nios II processor. Fortunately, most software
based on the Nios II hardware abstraction layer (HAL) works correctly without any
special accommodations for caches. However, some software must manage the cache
directly. For code that needs direct control over the cache, the Nios II architecture
provides facilities to perform the following actions:
標簽：
Nios
軟件開發
存儲器
上傳時間：
2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
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In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
標簽：
AXI4
379
wp
即插即用
上傳時間：
2013-11-11
上傳用戶：csgcd001
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The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
標簽：
PCI-X
XAPP
DIMM
708
上傳時間：
2013-11-24
上傳用戶：18707733937
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In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, However,here we try to cover a few of them.
標簽：
Efficient
Verilog
Digital
Coding
上傳時間：
2013-11-23
上傳用戶：我干你啊
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Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, However, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽：
Creating
Machines
Mentor
State
上傳時間：
2013-11-02
上傳用戶：xauthu
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Silicon Motion, Inc. has made best efforts to ensure that the information contained in this document is accurate andreliable. However, the information is subject to change without notice. No responsibility is assumed by SiliconMotion, Inc. for the use of this information, nor for infringements of patents or other rights of third parties.Copyright NoticeCopyright 2002, Silicon Motion, Inc. All rights reserved. No part of this publication may be reproduced, photocopied,or transmitted in any form, without the prior written consent of Silicon Motion, Inc. Silicon Motion, Inc. reserves theright to make changes to the product specification without reservation and without notice to our users
標簽：
GUIDELINES
LAYOUT
320
PCB
上傳時間：
2013-10-10
上傳用戶：manga135
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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標簽：
pci
PCB
設計規范
上傳時間：
2014-01-24
上傳用戶：s363994250
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There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
標簽：
CoolRunner-II
XAPP
904
LCD
上傳時間：
2013-12-17
上傳用戶：haiya2000
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This algorithm was developed by Professor Ronald L. Rivest of MIT and can be found presented in several languages. What I provide to you here is a C++ derivative of the original C implementation of Professor Rivets. The library code itself is platform-independant and has been tested in Redhat Linux. I ve included the sample code and makefile that I used for the Linux test. The demo, However, was written with Visual C++ 6 on a Windows 2000 platform.
標簽：
L.
Professor
algorithm
developed
上傳時間：
2014-12-21
上傳用戶：gonuiln
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Displaying a large bitmap file on a dialog box, in its original size, is quite difficult in the VC++ environment. However, it is possible to display a large bitmap to a predefined area of the dialog by using the StretchBlt( ) function.The major disadvantage of this is that the clarity of the image will be lost. Check out this article for displaying large bitmaps into the desired area of your dialog box in its original size with a scrolling technique used to show the entire bitmap. 滾動顯示位圖 在VC++環境下，在一個對話框中顯示一個原始尺寸的大小的位圖文件相當是困難的。然而,通過使用 StretchBlt()函數一個給定的區域顯示一個大的位圖是可能的。主要的缺點是圖像將會失真。看了這篇通過卷動技術顯示整個位圖技術的文章，你將能夠以它的原始尺寸在給定對話框的區域內顯示一個大位圖。 來源: http://www.codeguru.com/bitmap/ScrollBitmap.html
標簽：
Displaying
difficult
original
bitmap
上傳時間：
2014-01-05
上傳用戶：yiwen213
