Many applications use connection/object pool. A program may require a IMAP connection pool and LDAP connection pool. One could easily IMPLEMENT a IMAP connection pool, then take the existing code and IMPLEMENT a LDAP connection pool. The program grows, and now there is a need for a pool of threads. So just take the IMAP connection pool and convert that to a pool of threads (Copy, paste, find, replace????). Need to make some changes to the pool IMPLEMENTation? Not a very easy task, since the code has been duplicated in many places. Re-inventing source code is not an intelligent approach in an object oriented environment which encourages re-usability. It seems to make more sense to IMPLEMENT a pool that can contain any arbitrary type rather than duplicating code. How does one do that? The answer is to use type parameterization, more commonly referred to as templates.
標(biāo)簽： connection pool applications program
上傳時(shí)間： 2013-12-25
上傳用戶：playboys0
-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or IMPLEMENT it after contacting the author -- You can check the draft license at
標(biāo)簽： design combinational Shifter Barrel
上傳時(shí)間： 2014-12-21
上傳用戶：784533221
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and IMPLEMENT DSP algorithms targeting FPGAs. This intermediate workshop in IMPLEMENTing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design IMPLEMENTation tools. Through hands-on exercises, you will IMPLEMENT a design from algorithm concept to verification.
標(biāo)簽： introduction workshop provides advanced
上傳時(shí)間： 2014-12-06
上傳用戶：sammi
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for IMPLEMENTing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that IMPLEMENT such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates IMPLEMENTing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
Functional_Verification_Coverage_Measurement_and_Analysis。 Author:Andrew Piziali. The component inlcuding the functionla coverage, code coverge mearsurement and analysise. And describe the particular IMPLEMENT ways on the details.
標(biāo)簽： Functional_Verification_Coverage_ Measurement_and_Analysis component Piziali
上傳時(shí)間： 2013-12-25
上傳用戶：zhouchang199
OpenCV means Intel® Open Source Computer Vision Library. It is a collection of C functions and a few C++ classes that IMPLEMENT some popular Image Processing and Computer Vision algorithms. OpenCV has cross-platform middle-to-high level API that consists of a few hundreds (>300) C functions. It does not rely on external libraries, though it can use some when it is possible. OpenCV is free for both non-commercial and commercial use (see the license for details). OpenCV provides transparent interface to Intel® Integrated Performance Primitives (IPP). That is, it loads automatically IPP libraries optimized for specific processor at runtime, if they are available. More information about IPP can be retrieved at http://www.intel.com/software/products/ipp/index.htm -------------------------------------------------------------------------------- 本文是opencv的入門(mén)教程
標(biāo)簽： collection functions Computer Library
上傳時(shí)間： 2015-09-12
上傳用戶：zhangyi99104144
％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,the phase of the ％incoming signal is locked and the signal is demodulated.This scheme ％is used in PM and FM as well. ％We will IMPLEMENT it by using a closed loop system.Control systems ％techniques are applied here.
標(biāo)簽： phase w.r.t oscillator modulated
上傳時(shí)間： 2015-09-28
上傳用戶：zhangzhenyu
With the release of PHP 5 web developers need a guide to developing with PHP 5 to both learn its complex new features and more fully IMPLEMENT the long-standing features on which PHP s success is built. PHP 5 in Practice is a reference guide that provides developers with easy-to-use and easily extensible code to solve common PHP problems. It focuses on providing real code solutions to problems, allowing the reader to learn by seeing exactly what is happening behind the scenes to get your solution. Because a real-life situation will rarely match the book s example problems precisely, PHP 5 in Practice explains the solution well enough that you will understand it and can learn how to truly solve your own problem.
標(biāo)簽： developers developing PHP release
上傳時(shí)間： 2013-12-17
上傳用戶：xzt
Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to IMPLEMENTing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to IMPLEMENT the CORDIC algorithm.
標(biāo)簽： representation Magnitude the magnitude
上傳時(shí)間： 2013-12-24
上傳用戶：金宜
主要特點(diǎn) * Flexible finite element space construction based template element library 基于模板單元庫(kù)靈活的構(gòu)造有限元空間 * Convenient facilities to IMPLEMENT mesh adaption 很方便的進(jìn)行網(wǎng)格加密和稀疏化 * Multi-mesh operation supported 支持多套網(wǎng)格操作 需要有一定的有限元基礎(chǔ)和C++語(yǔ)言基礎(chǔ)，最好在linux平臺(tái)下用。 http://162.105.68.168/AFEPack/
標(biāo)簽： element construction Flexible template
上傳時(shí)間： 2014-11-21
上傳用戶：qq1604324866
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
<big id="yrsur"></big>