闡述了軌道交通列車定位技術(shù)。介紹了在軌道交通系統(tǒng)中列車定位技術(shù)的功能，國內(nèi)外軌道交通中主要采用的列車定位方法，重點論述了幾種主要定位技術(shù)，并從定位精度、閉塞制式、維護(hù)投資成本、抗干擾等方面進(jìn)行分析比較。提出目前軌道交通定位技術(shù)應(yīng)綜合運用，取長補短，多種方法相互融合，才能滿足軌道交通中對安全可靠性的要求。 Abstract: Rail train positioning technology is described. The paper introduces the funetions of the train positioning technology in the rail transit system， the main methods of train positioning do mestic and international rail， and focuses on several key methods， analyzes and compares from the positioning accuracy， block system, maintenance and investment cost， interference and so on， suggested that the current rail positioning technology should be integrated use of positioning method of meriging， learn from each other， to meet the reliability requirements of rail safety.
上傳時間： 2013-11-25
上傳用戶：franktu
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過同步字頭攜帶相關(guān)碼的方法來實現(xiàn)同步，但對于快跳頻來說，由于是一跳或者多跳傳輸一個調(diào)制符號，難以攜帶相關(guān)碼。對此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時間： 2013-11-23
上傳用戶：mpquest
ARM embeded system designer,周立功版本，國內(nèi)較有名的一版。
標(biāo)簽： designer embeded system ARM
上傳時間： 2013-10-31
上傳用戶：zaizaibang
提出了一種以ARM微處理器為控制核心的遠(yuǎn)程無線視頻監(jiān)控終端的設(shè)計方案，其監(jiān)控終端的硬件設(shè)計包括視頻采集處理、中央管理控制、無線傳輸3個模塊。并給出了監(jiān)控終端的軟件開發(fā)平臺和開發(fā)模式的系統(tǒng)啟動代碼、嵌入式Linux系統(tǒng)移植以及驅(qū)動程序和應(yīng)用程序。測試結(jié)果表明，該監(jiān)控終端設(shè)計方案合理、有效，基本滿足監(jiān)控需求。 Abstract: A remote wireless video monitoring terminal design， which uses ARM microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
標(biāo)簽： ARM 遠(yuǎn)程無線 視頻監(jiān)控 終端設(shè)計
上傳時間： 2013-11-13
上傳用戶：wanqunsheng
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時間： 2013-10-11
上傳用戶：yuchunhai1990
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計及在設(shè)計初級產(chǎn)生最佳的I/O引腳規(guī)劃，并可透過FSP做系統(tǒng)化的設(shè)計規(guī)劃，同時整合logic、schematic、PCB同步規(guī)劃單個或多個FPGA pin的最佳化及l(fā)ayout placement，借由整合式的界面以減少重復(fù)在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。 Specifying Design Intent 在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內(nèi)的包裝，預(yù)先讓我們同步規(guī)劃FPGA設(shè)計及在PCB的placement。
標(biāo)簽： Allegro Planner System FPGA
上傳時間： 2013-11-06
上傳用戶：wwwe
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時間： 2013-11-11
上傳用戶：gundamwzc
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
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