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IN-system-Debugger

  • VHDL,Verilog,System verilog比較

      本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog,System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

    標(biāo)簽: Verilog verilog System VHDL

    上傳時(shí)間: 2013-10-16

    上傳用戶:牛布牛

  • 電臺(tái)維修模擬訓(xùn)練系統(tǒng)設(shè)計(jì)方法研究

    Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures, follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process, it can not only be used in teaching, but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.

    標(biāo)簽: 電臺(tái)維修 模擬訓(xùn)練 方法研究 系統(tǒng)設(shè)計(jì)

    上傳時(shí)間: 2013-11-19

    上傳用戶:3294322651

  • High-Speed Digital System Design

    Introduce High-Speed Digital System Design.

    標(biāo)簽: High-Speed Digital Design System

    上傳時(shí)間: 2013-10-20

    上傳用戶:gps6888

  • 基于System Generator的數(shù)字下變頻設(shè)計(jì)

    Xilinx公司推出的DSP設(shè)計(jì)開(kāi)發(fā)工具System Generator是在Matlab環(huán)境中進(jìn)行建模,是DSP高層系統(tǒng)設(shè)計(jì)與Xilinx FPGA之間實(shí)現(xiàn)的“橋梁”。在分析了FPGA傳統(tǒng)級(jí)設(shè)計(jì)方法的基礎(chǔ)上,提出了基于System Generator的系統(tǒng)級(jí)設(shè)計(jì)新方法,并應(yīng)用新方法設(shè)計(jì)驗(yàn)證了一套數(shù)字下變頻系統(tǒng),通過(guò)仿真和實(shí)驗(yàn)結(jié)果驗(yàn)證了該方法的有效性和準(zhǔn)確性。

    標(biāo)簽: Generator System 數(shù)字 變頻設(shè)計(jì)

    上傳時(shí)間: 2013-11-18

    上傳用戶:小草123

  • 提高在噪聲環(huán)境下的磁卡讀寫器(MCR)系統(tǒng)

    Abstract: Most magnetic read head data sheets do not fully specify the frequency-dependent components andare often vague when specifying other key parameters. In some cases, the specifications of two very similarheads from two different manufacturers might be quite different in terms of parameters specified and omitted.The limitations in the data sheets make designing an optimum card reading system unnecessarily difficult andtime consuming. This document outlines a strategy to overcome the above shortcomings and offers guidelinesto overcome the noise issues.

    標(biāo)簽: MCR 噪聲環(huán)境 磁卡讀寫器

    上傳時(shí)間: 2013-11-13

    上傳用戶:dysyase

  • MEMS麥克風(fēng)有助于提高系統(tǒng)設(shè)計(jì)效率

    A MEMS microphone IC is unique among Analog Devices, Inc., products in that its input is an acoustic pressure wave. For this reason, some specifications included in the data sheets for these parts may not be familiar, or familiar specifications may be applied in unfamiliar ways. This application note explains the specifica-tions and terms found in MEMS microphone data sheets so that the microphone can be appropriately designed into a system.

    標(biāo)簽: MEMS 麥克風(fēng) 系統(tǒng)設(shè)計(jì) 效率

    上傳時(shí)間: 2013-10-31

    上傳用戶:masochism

  • 精密DAC和看門狗提高模擬輸出安全

    Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-scale (or pin-programmable midscale) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.

    標(biāo)簽: DAC 精密 看門狗 模擬

    上傳時(shí)間: 2013-10-17

    上傳用戶:sjb555

  • 數(shù)字集成電路設(shè)計(jì)Digital Integrated Circuit Design

      This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.

    標(biāo)簽: Integrated Digital Circuit Design

    上傳時(shí)間: 2013-11-04

    上傳用戶:life840315

  • 簡(jiǎn)化精密測(cè)量的高輸入阻抗ADC

      High input impedance and a wide input range are twohighly desirable features in a precision analog-to-digitalconverter, and the LTC®2449 delta-sigma ADC has both.With just a few external components, the LTC2449 formsan exceptional measurement system with very high inputimpedance and an input range that extends 300mV beyondthe supply rails.

    標(biāo)簽: ADC 精密測(cè)量 高輸入阻抗

    上傳時(shí)間: 2013-11-02

    上傳用戶:ywcftc277

  • RF至數(shù)字接收器的信號(hào)鏈噪聲分析

      Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.

    標(biāo)簽: 數(shù)字接收器 信號(hào)鏈 噪聲分析

    上傳時(shí)間: 2014-12-05

    上傳用戶:cylnpy

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