C IN a Nutshell is the perfect companion to K&R, and destINed to be the most reached-for reference on your desk.
標簽： reached-for companion the reference
上傳時間： 2015-07-26
上傳用戶：kr770906
his project was built and tested with WINAVR-20060125. Make sure the MCU target defINe IN the Makefiles corresponds to the AVR you are usINg!! To build the code, just INstall WINAVR and run "make" from the console IN echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is workINg FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is runnINg on that!
標簽： the 20060125 project WINAVR
上傳時間： 2014-10-10
上傳用戶：yan2267246
函數ReadDat()實現從文件ENG.IN中讀取一篇英文文章，存入到字符串數組xx中；請編制函數encryptChar()，按給定的替代關系對數組xx中的所有字符進行替代，仍存入數組xx的對應的位置上，最后調用函數WriteDat()把結果xx輸出到文件PS10.DAT中。
上傳時間： 2015-07-26
上傳用戶：com1com2
Ultra.Wideband.Signals.and.Systems.IN.Communication.EngINeerINg.eBook-kB代碼
標簽： Communication EngINeerINg Wideband eBook-kB
上傳時間： 2015-07-26
上傳用戶：hxy200501
Part1 of CPRM association document, CPRM is used IN copyright protection, which is necessary IN SD system
標簽： CPRM association protection copyright
上傳時間： 2014-12-21
上傳用戶：zsjzc
Part2 of CPRM data document, CPRM is for copyright protection IN SD system
標簽： CPRM protection copyright document
上傳時間： 2015-07-26
上傳用戶：zmy123
Part3 of CPRM data document, CPRM is for copyright protection IN SD system
標簽： CPRM protection copyright document
上傳時間： 2015-07-26
上傳用戶：aappkkee
Part4 of CPRM data document, CPRM is for copyright protection IN SD system
標簽： CPRM protection copyright document
上傳時間： 2015-07-26
上傳用戶：671145514
關于FPGA流水線設計的論文 This work INvestigates the use of very deep pipelINes for implementINg circuits IN FPGAs, where each pipelINe stage is limited to a sINgle FPGA logic element (LE). The architecture and VHDL design of a parameterized INteger array multiplier is presented and also an IEEE 754 compliant 32-bit floatINg-poINt multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit INteger multiplier achieves a frequency of 266MHz, while the floatINg poINt unit reaches 235MHz, performINg 235 MFLOPS IN an FPGA. Additional cells are INserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique IN real designs are also addressed.
標簽： INvestigates implementINg pipelINes circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This the first cellphone worm with source code available IN the world ! Do you can modify, rename, delete, INsert any code...
標簽： the cellphone available source
上傳時間： 2015-08-03
上傳用戶：xiaohuanhuan
