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EEPROM為ATMEL公司的AT24C01A。單片機(jī)為ATMEL公司的AT89C51。2. 軟件說明 C語言為Franklin C V3.2。將源程序另存為testi2c.c，用命令C51 testi2c.cL51 TESTI2C.OBJOHS51 TESTI2C編譯，連接，得到TESTI2C.HEX文件，即可由編程器讀入并進(jìn)行寫片，實(shí)驗(yàn)。3．源程序#INCLUDE <reg51.h>#INCLUDE <intrins.h> #define uchar unsigned char#define uint unsigned int#define AddWr 0xa0 /*器件地址選擇及寫標(biāo)志*/#define AddRd 0xa1 /*器件地址選擇及讀標(biāo)志*/#define Hidden 0x0e /*顯示器的消隱碼*/
標(biāo)簽：
C51
I2C
單片機(jī)
C語言
上傳時(shí)間：
2013-10-09
上傳用戶：hjshhyy
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INCLUDE "macrodefine.h"#INCLUDE "lpc2294.h"
//ADS1210初始化子程序void AD_Init(void){ Delayus(2); SPI1_Communation(0x64); SPI1_Communation(0x72); //單極性，SDOUT獨(dú)立，先MSB，REF使用內(nèi)部 SPI1_Communation(0x20); //自校準(zhǔn)模式，增益1，通道0 SPI1_Communation(0x87); //TURBO=16， SPI1_Communation(0xa0); //數(shù)據(jù)更新率100}//讀取ADS1210轉(zhuǎn)換結(jié)果子程序uint32 Read_AD_Data(void){ uint8 i=0; uint8 Data_Temp[3]; uint32 Result_HEX=0; Delayus(1); SPI1_Communation(0xc0); for(i=0;i<3;i++) { Data_Temp[i] =SPI1_Communation(0xff); }
標(biāo)簽：
ADS
1210
1211
C程序
上傳時(shí)間：
2013-10-10
上傳用戶：suicone
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs INCLUDE:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-13
上傳用戶：瓦力瓦力hong
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This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems INCLUDE train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications INCLUDE
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標(biāo)簽：
FPGA
安全系統(tǒng)
上傳時(shí)間：
2013-11-05
上傳用戶：維子哥哥
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Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These INCLUDE (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
標(biāo)簽：
FPGA
電源
上傳時(shí)間：
2013-11-10
上傳用戶：iswlkje
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UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl
This zip file contains the following folders:
\vhdl_source -- Source VHDL files:
uart.vhd - top level file
txmit.vhd - transmit portion of uart
rcvr.vhd - - receive portion of uart
\vhdl_testfixture -- VHDL Testbench files. This files only INCLUDE the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level VHDL
file or a schematic. This folder contains the following files:
txmit_tb.vhd -- Test bench for txmit.vhd.
rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽：
UART
Xilinx
VHDL
參考設(shè)計(jì)
上傳時(shí)間：
2013-11-07
上傳用戶：jasson5678
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A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These INCLUDE the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
標(biāo)簽：
PICMG_COM
COMe
上傳時(shí)間：
2013-11-05
上傳用戶：Wwill
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The CC1101 is a low-cost sub- 1 GHztransceiver designed for very low-powerwireless applications. The circuit is mainlyintended for the ISM (Industrial, Scientific andMedical) and SRD (Short Range Device)frequency bands at 315, 433, 868, and 915MHz, but can easily be programmed foroperation at other frequencies in the 300-348MHz, 387-464 MHz and 779-928 MHz bands.CC1101 is an improved and code compatibleversion of the CC1100 RF transceiver. Themain improvements on the CC1101 INCLUDE:
標(biāo)簽：
1110
CC
片上系統(tǒng)
方案
上傳時(shí)間：
2013-11-12
上傳用戶：363186
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Linear Technology offers some of the highest performance RF and signal chain solutions for wireless and cellularinfrastructure. These products support worldwide standards including, LTE, WiMAX, GSM,W-CDMA, TD-SCDMA,CDMA, and CDMA2000. Other wireless systems INCLUDE broadband microwave data links, secure communications,satellite receivers, broadband wireless access, wireless broadcast systems, RFID readers and cable infrastructure
標(biāo)簽：
無線
方案
上傳時(shí)間：
2013-11-04
上傳用戶：kiklkook
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also INCLUDEs an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 INCLUDE up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽：
Cortex-M
1850
LPC
內(nèi)核微控制器
上傳時(shí)間：
2014-12-31
上傳用戶：zhuoying119
