This document is a quick reference to some of the formulas and important INFOrmation related to optical technologies. It focuses on decibels (dB), decibels per milliwatt (dBm), attenuation and measurements, and provides an introduction to optical fibers.
上傳時間： 2013-10-17
上傳用戶：libenshu01
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過同步字頭攜帶相關(guān)碼的方法來實現(xiàn)同步，但對于快跳頻來說，由于是一跳或者多跳傳輸一個調(diào)制符號，難以攜帶相關(guān)碼。對此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization INFOrmation， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization INFOrmation is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時間： 2013-11-23
上傳用戶：mpquest
The INFOrmation in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
標(biāo)簽： 技術(shù)資料
上傳時間： 2013-10-08
上傳用戶：stewart·
This book contains INFOrmation obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and INFOrmation, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.
上傳時間： 2014-12-31
上傳用戶：PresidentHuang
飛思卡爾智能車的舵機(jī)測試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative INFOrmation */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環(huán)電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機(jī)初始化 PWMCTL_CON01=1; //0和1聯(lián)合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對齊輸出模式 PWMCNT01 = 0; //計數(shù)器清零； PWMPOL_PPOL1=1; //先輸出高電平，計數(shù)到DTY時，反轉(zhuǎn)電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時間為1.5ms; PWME_PWME1 = 1;
上傳時間： 2013-11-04
上傳用戶：狗日的日子
IBIS 模型在做類似板級SI 仿真得到廣泛應(yīng)用。在做仿真的初級階段，經(jīng)常對于ibis 模型的描述有些疑問，只知道把模型拿來轉(zhuǎn)換為軟件所支持的格式或者直接使用，而對于IBIS 模型里面的數(shù)據(jù)描述什么都不算很明白，因此下面的一些描述是整理出來的一點對于ibis 的基本理解。在此引用很多presention來描述ibis 內(nèi)容（有的照抄過來，阿彌陀佛，不要說抄襲，只不過習(xí)慣信手拈來說明一些問題），僅此向如muranyi 等ibis 先驅(qū)者致敬。本文難免有些錯誤或者考慮不周，隨時歡迎進(jìn)行討論并對其進(jìn)行修改！IBIS 模型的一些基本概念I(lǐng)BIS 這個詞是Input/Output buffer INFOrmation specification 的縮寫。本文是基于IBIS ver3.2 所撰寫出來（www.eigroup.org/IBIS/可下載到各種版本spec）,ver4.2增加很多新特性，由于在目前設(shè)計中沒用到不予以討論。。。在業(yè)界經(jīng)常會把spice 模型描述為transistor model 是因為它描述很多電路細(xì)節(jié)問題。而把ibis 模型描述為behavioral model 是因為它并不象spice 模型那樣描述電路的構(gòu)成，IBIS 模型描述的只不過是電路的一種外在表現(xiàn)，象個黑匣子一樣，輸入什么然后就得到輸出結(jié)果，而不需要了解里面驅(qū)動或者接收的電路構(gòu)成。因此有所謂的garbage in, garbage out，ibis 模型的仿真精度依賴于模型的準(zhǔn)確度以及考慮的worse case，因此無論你的模型如何精確而考慮的worse case 不周全或者你考慮的worse case 如何周全而模型不精確，都是得不到較好的仿真精度。
上傳時間： 2013-10-16
上傳用戶：zhouli
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more INFOrmation on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時間： 2013-11-05
上傳用戶：超凡大師
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For INFOrmation on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
標(biāo)簽： Xilinx XAPP XSVF 503
上傳時間： 2015-01-02
上傳用戶：時代將軍
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This INFOrmation can be usedfor partial reconfiguration or partial readback.
標(biāo)簽： Spartan XAPP 452 架構(gòu)
上傳時間： 2013-11-16
上傳用戶：qingdou
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides INFOrmation on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標(biāo)簽： Spartan-XL Express XAPP FPGA
上傳時間： 2015-01-02
上傳用戶：nanxia
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