This document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are Intended to correspond to theheading or table affected in the general hardware speciÞcation.Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table B.
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is Intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyIntended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
The CC1101 is a low-cost sub- 1 GHztransceiver designed for very low-powerwireless applications. The circuit is mainlyIntended for the ISM (Industrial, Scientific andMedical) and SRD (Short Range Device)frequency bands at 315, 433, 868, and 915MHz, but can easily be programmed foroperation at other frequencies in the 300-348MHz, 387-464 MHz and 779-928 MHz bands.CC1101 is an improved and code compatibleversion of the CC1100 RF transceiver. Themain improvements on the CC1101 include:
Radio frequency (RF) can be a complex subject to navigate, but it does not have to be. If you are just getting started with radios or maybe you cannot find that old reference book about antenna aperture, this guide can help. It is Intended to provide a basic understanding of RF technology, as well act as a quick reference for those who “know their stuff” but may be looking to brush up on that one niche term that they never quite understood. This document is also a useful reference for Maxim’s products and data sheets, an index to deeper analysis found in our application notes, and a general reference for all things RF.
Radio frequency (RF) can be a complex subject to navigate, but it does not have to be. If you are just getting started with radios or maybe you cannot find that old reference book about antenna aperture, this guide can help. It is Intended to provide a basic understanding of RF technology, as well act as a quick reference for those who “know their stuff” but may be looking to brush up on that one niche term that they never quite understood. This document is also a useful reference for Maxim’s products and data sheets, an index to deeper analysis found in our application notes, and a general reference for all things RF.
This book is about the digital logic design of microprocessors. It is Intended to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles are applied in the building of complex microprocessor circuits using current technologies.
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is Intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are Intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is Intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
項目描述: slsnif is a serial port logging utility. It listens to the specified serial port and logs all data going through this port in both directions. Serial line sniffer是一個串行端口記錄工具。它監聽指定的串行端口并記錄所有通過這個端口的兩個方向的數據。 來源：http://freshmeat.net slsnif是一個串行端口日志工具。它監聽特殊的串口，記錄所有通過這具串口的兩個方向的數據。 類別: Development Status: 5 - Production/StableEnvironment: Console (Text Based)Intended Audience: DevelopersLicense: GNU General Public License (GPL)Operating System: LinuxProgramming Language: CTopic: Communications, Debuggers
項目描述: slsnif is a serial port logging utility. It listens to the specified serial port and logs all data going through this port in both directions. Serial line sniffer是一個串行端口記錄工具。它監聽指定的串行端口并記錄所有通過這個端口的兩個方向的數據。 來源：http://freshmeat.net slsnif是一個串行端口日志工具。它監聽特殊的串口，記錄所有通過這具串口的兩個方向的數據。 類別: Development Status: 5 - Production/StableEnvironment: Console (Text Based)Intended Audience: DevelopersLicense: GNU General Public License (GPL)Operating System: LinuxProgramming Language: CTopic: Communications, Debuggers
