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高速數(shù)字系統(tǒng)設(shè)計下載pdf:High-Speed Digital SystemDesign—A Handbook ofInterconnect Theory and DesignPracticesStephen H. HallGarrett W. HallJames A. McCallA Wiley-Interscience Publication JOHN WILEY & SONS, INC.New York • Chichester • Weinheim • Brisbane • Singapore • TorontoCopyright © 2000 by John Wiley & Sons, Inc.speeddigital systems at the platform level. The book walks the reader through everyrequired concept, from basic transmission line theory to digital timing analysis, high-speedmeasurement techniques, as well as many other topics. In doing so, a unique balancebetween theory and practical applications is achieved that will allow the reader not only tounderstand the nature of the problem, but also provide practical guidance to the solution.The level of theoretical understanding is such that the reader will be equipped to see beyondthe immediate practical application and solve problems not contained within these pages.Much of the information in this book has not been needed in past digital designs but isabsolutely necessary today. Most of the information covered here is not covered in standardcollege curricula, at least not in its focus on digital design, which is arguably one of the mostsignificant industries in electrical engineering.The focus of this book is on the design of robust high-volume, high-speed digital productssuch as computer systems, with particular attention paid to computer busses. However, thetheory presented is applicable to any high-speed digital system. All of the techniquescovered in this book have been applied in industry to actual digital products that have beensuccessfully produced and sold in high volume.Practicing engineers and graduate and undergraduate students who have completed basicelectromagnetic or microwave design classes are equipped to fully comprehend the theorypresented in this book. At a practical level, however, basic circuit theory is all thebackground required to apply the formulas in this book.
標簽：
高速數(shù)字
系統(tǒng)設(shè)計
上傳時間：
2013-10-26
上傳用戶：縹緲
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This document provides practical, common guidelines for incorporating PCI Express Interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes Interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and Interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical Interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express Interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the Interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the Interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and Interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標簽：
pci
PCB
設(shè)計規(guī)范
上傳時間：
2013-10-15
上傳用戶：busterman
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PCI ExpressTM is the third generation of PCI (PeripheralComponent Interconnect) technology used to connect I/Operhipheral devices in computer systems. It is intended asa general purpose I/O device Interconnect that meets theneeds of a wide variety of computing platforms such asdesktop, mobile, server and communications. It alsospecifies the electrical and mechanical attributes of thebackplane, connectors and removable cards in thesesystems.
標簽：
Express
PCI
電源解決方案
上傳時間：
2013-11-17
上傳用戶：squershop
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The latest generation of Texas Instruments (TI) boardmountedpower modules utilizes a pin Interconnect technologythat improves surface-mount manufacturability.These modules are produced as a double-sided surfacemount(DSSMT) subassembly, yielding a case-less constructionwith subcomponents located on both sides of theprinted circuit board (PCB). Products produced in theDSSMT outline use the latest high-efficiency topologiesand magnetic-component packaging. This providescustomers with a high-efficiency, ready-to-use switchingpower module in a compact, space-saving package. Bothnonisolated point-of-load (POL) switching regulators andthe isolated dc/dc converter modules are being producedin the DSSMT outline.TI’s plug-in power product line offers power modules inboth through-hole and surface-mount packages. The surfacemountmodules produced in the DSSMT outline use asolid copper Interconnect with an integral solder ball fortheir
標簽：
電源模塊
可制造性
表面貼裝
上傳時間：
2013-10-10
上傳用戶：1184599859
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采用UART做LIN總線的從節(jié)點應用:本應用例使用SPMC75F2313A和通用LIN Bus收發(fā)器TJA1020（或ATA6661）實現(xiàn)LIN（Local Interconnect Network）是低成本的汽車網(wǎng)絡(luò)的傳輸。1.2 LIN Bus規(guī)范LIN 是低成本網(wǎng)絡(luò)中的汽車通訊協(xié)議標準，LIN（Local Interconnect Network）是低成本的汽車網(wǎng)絡(luò)，它是現(xiàn)有多種汽車網(wǎng)絡(luò)在功能上的補充由于能夠提高質(zhì)量、降低成本，LIN 將是在汽車中使用汽車分級網(wǎng)絡(luò)的啟動因素。LIN 的標準化將簡化多種現(xiàn)存的多點解決方案且將降低在汽車電子領(lǐng)域中的開發(fā)生產(chǎn)服務和后勤成本。LIN 標準包括傳輸協(xié)議規(guī)范、傳輸媒體規(guī)范、開發(fā)工具接口規(guī)范和用于軟件編程的接口LIN在硬件和軟件上保證了網(wǎng)絡(luò)節(jié)點的互操作性并有可預測EMC的功能。
標簽：
UART
LIN
總線
節(jié)點
上傳時間：
2013-11-19
上傳用戶：
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采用UART做LIN總線的主節(jié)點應用:本應用例使用SPMC75F2313A和通用LIN Bus收發(fā)器TJA1020（或ATA6661）實現(xiàn)LIN（Local Interconnect Network）是低成本的汽車網(wǎng)絡(luò)的傳輸。1.2 LIN Bus規(guī)范LIN 是低成本網(wǎng)絡(luò)中的汽車通訊協(xié)議標準，LIN（Local Interconnect Network）是低成本的汽車網(wǎng)絡(luò)，它是現(xiàn)有多種汽車網(wǎng)絡(luò)在功能上的補充由于能夠提高質(zhì)量、降低成本，LIN 將是在汽車中使用汽車分級網(wǎng)絡(luò)的啟動因素。LIN 的標準化將簡化多種現(xiàn)存的多點解決方案且將降低在汽車電子領(lǐng)域中的開發(fā)生產(chǎn)服務和后勤成本。LIN 標準包括傳輸協(xié)議規(guī)范、傳輸媒體規(guī)范、開發(fā)工具接口規(guī)范和用于軟件編程的接口LIN在硬件和軟件上保證了網(wǎng)絡(luò)節(jié)點的互操作性并有可預測EMC的功能。
標簽：
UART
LIN
總線
主節(jié)點
上傳時間：
2013-10-15
上傳用戶：AISINI005
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多功能高集成外圍器件6. 1 多功能高集成外圍器件82371PCI的英文名稱：Peripheral Component Interconnect （外圍部件互聯(lián)PCI總線）；82371是PCI總線組件。ISA是：Industry Standard Architecture（工業(yè)標準體系結(jié)構(gòu)）IDE是 （Integrated Device Electronics）集成電路設(shè)備簡稱PIIX4PIIX4器件（芯片）的特點1、是一種支持Pentium和PentiumII微處理器的部件。2、82371對ISA橋來說，是一種多功能PCI總線。3、對可移動性和桌面深綠色環(huán)境均提供支持。4、電源管理邏輯。5、被集成化的IDE控制器。6、增強了性能的DMA控制器。 （7）基于兩個82C59的中斷控制器。（8）基于82C54芯片的定時器。（9）USB（Universal Serial Bus）通用串行總線。（10）SMBus系統(tǒng)管理總線。（11）實時時鐘（12）順應Microsoft Win95所需的功能其芯片的邏輯框圖如圖6-1所示。 PIIX4芯片邏輯框圖6.1.1 概述PIIX4芯片是一個多功能的PCI器件，圖6-2 是82371在系統(tǒng)中扮演的角色。（續(xù)上圖）1. PCI與EIO之間的橋（PIIX4芯片）橋是不對程的，是各類不同標準總線與PCI總線連接，82371AB橋也可理解為一種總線轉(zhuǎn)換譯碼器和控制器，橋內(nèi)包含復雜的協(xié)議總線信號和緩沖器。(1).在PCI系統(tǒng)內(nèi)，當PIIX4操作時，它總是作為系統(tǒng)內(nèi)各種模塊的主控設(shè)備，如USB和DMA控制器、IDE總線和分布式DMA的主控設(shè)備等，而且總是以ISA主控設(shè)備的名義出現(xiàn)。(2). 在向ISA總線或IDE總線進行傳送操作的傳送周期期間作為從屬設(shè)備使用，并對內(nèi)部寄存器譯碼。PIIX4芯片（橋）的配置(1).可以把PIIX4芯片配置成整個ISA總線，或ISA總線的子集，也可擴展成EIO總線。在使用EIO總線時，可以把未使用的信號配置成通用的輸入和輸出。(2).PIIX4可直接驅(qū)動5個ISA插槽；(3).能提供字節(jié)-交換邏輯、I/O的恢復支持、等待狀態(tài)的生成以及SYSCLK的生成。(4).提供X-BUS鍵盤控制器芯片、BIOS芯片、實時時鐘芯片、二級微程序器等的選擇。2. IDE接口（總線主控設(shè)備的權(quán)利和同步DMA方式）IDE接口為4個IDE的設(shè)備提供支持，比如IDE接口的硬盤和CD-ROM等。注意：目前硬盤接口有5類：IDE、SCSI、Fibre Channel、IEEE1394和USB等。IDE口幾乎在PC機最多，因為便宜。SCSI多用于服務器和集群機。IDE的PIO IDE速率：14MB/s；而總線主控設(shè)備IDE的速率：33MB/s在PIIX4芯片的IDE系統(tǒng)內(nèi)，配有兩個各次獨立的IDE信號通道。3. 具有兼容性的模塊—DMA、定時器/計數(shù)器、中斷控制器等（1）在PIIX4內(nèi)的兩各82C37 DMA控制器經(jīng)邏輯的組合，產(chǎn)生7個獨立的可編程通道。通道[0：3]是通過與8個二進位的硬件連線實現(xiàn)的。通過以字節(jié)為單位的計數(shù)進行傳送。而通道[5：7]是通過16個二進位的連線實現(xiàn)的，以字為單位的計數(shù)進行傳送。（2）DMA控制器還能通過PCI總線，處理舊的DMA的兩個不同的方法提供支持。（3）計數(shù)/定時器模塊在功能上與82C54等價。（4）中斷控制器與ISA兼容，其功能是兩個82C59的功能之和。
標簽：
多功能
外圍器件
集成
上傳時間：
2013-11-19
上傳用戶：3到15
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The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
標簽：
MPC
106
PCI
存儲器
上傳時間：
2013-11-04
上傳用戶：as275944189
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計算機部件要具有通用性，適應不同系統(tǒng)與不同用戶的需求，設(shè)計必須模塊化。計算機部件產(chǎn)品(模塊)供應出現(xiàn)多元化。模塊之間的聯(lián)接關(guān)系要標準化，使模塊具有通用性。模塊設(shè)計必須基于一種大多數(shù)廠商認可的模塊聯(lián)接關(guān)系，即一種總線標準。總線的標準總線是一類信號線的集合是模塊間傳輸信息的公共通道，通過它，計算機各部件間可進行各種數(shù)據(jù)和命令的傳送。為使不同供應商的產(chǎn)品間能夠互換，給用戶更多的選擇，總線的技術(shù)規(guī)范要標準化。總線的標準制定要經(jīng)周密考慮，要有嚴格的規(guī)定。總線標準（技術(shù)規(guī)范）包括以下幾部分：機械結(jié)構(gòu)規(guī)范：模塊尺寸、總線插頭、總線接插件以及按裝尺寸均有統(tǒng)一規(guī)定。功能規(guī)范：總線每條信號線（引腳的名稱）、功能以及工作過程要有統(tǒng)一規(guī)定。電氣規(guī)范：總線每條信號線的有效電平、動態(tài)轉(zhuǎn)換時間、負載能力等。總線的發(fā)展情況S-100總線：產(chǎn)生于1975年，第一個標準化總線，為微計算機技術(shù)發(fā)展起到了推動作用。IBM-PC個人計算機采用總線結(jié)構(gòu)（Industry Standard Architecture, ISA)并成為工業(yè)化的標準。先后出現(xiàn)8位ISA總線、16位ISA總線以及后來兼容廠商推出的EISA（Extended ISA)32位ISA總線。為了適應微處理器性能的提高及I/O模塊更高吞吐率的要求，出現(xiàn)了VL-Bus(VESA Local Bus)和PCI(Peripheral Component Interconnect,PCI）總線。適合小型化要求的PCMCIA(Personal Computer Memory Card International Association)總線，用于筆記本計算機的功能擴展。總線的指標計算機主機性能迅速提高,各功能模塊性能也要相應提高,這對總線性能提出更高的要求。總線主要技術(shù)指標有幾方面：總線寬度：一次操作可以傳輸?shù)臄?shù)據(jù)位數(shù)，如S100為8位，ISA為16位，EISA為32位，PCI-2可達64位。總線寬度不會超過微處理器外部數(shù)據(jù)總線的寬度。總數(shù)工作頻率：總線信號中有一個CLK時鐘，CLK越高每秒鐘傳輸?shù)臄?shù)據(jù)量越大。ISA、EISA為8MHz，PCI為33.3MHz, PCI-2可達達66.6MHz。單個數(shù)據(jù)傳輸周期：不同的傳輸方式，每個數(shù)據(jù)傳輸所用CLK周期數(shù)不同。ISA要2個，PCI用1個CLK周期。這決定總線最高數(shù)據(jù)傳輸率。5. 總線的分類與層次系統(tǒng)總線：是微處理器芯片對外引線信號的延伸或映射，是微處理器與片外存儲器及I/0接口傳輸信息的通路。系統(tǒng)總線信號按功能可分為三類：地址總線（Where）：指出數(shù)據(jù)的來源與去向。地址總線的位數(shù)決定了存儲空間的大小。系統(tǒng)總線：數(shù)據(jù)總線（What）提供模塊間傳輸數(shù)據(jù)的路徑，數(shù)據(jù)總線的位數(shù)決定微處理器結(jié)構(gòu)的復雜度及總體性能。控制總線（When）：提供系統(tǒng)操作所必需的控制信號，對操作過程進行控制與定時。擴充總線：亦稱設(shè)備總線，用于系統(tǒng)I/O擴充。與系統(tǒng)總線工作頻率不同，經(jīng)接口電路對系統(tǒng)總統(tǒng)信號緩沖、變換、隔離，進行不同層次的操作（ISA、EISA、MCA)局部總線：擴充總線不能滿足高性能設(shè)備（圖形、視頻、網(wǎng)絡(luò)）接口的要求，在系統(tǒng)總線與擴充總線之間插入一層總線。由于它經(jīng)橋接器與系統(tǒng)總線直接相連，因此稱之為局部總線（PCI）。
標簽：
微型計算機
總線
上傳時間：
2013-11-09
上傳用戶：nshark
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and Interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
