-
Stellaris(群星)單片機加上32KB串行SRAM(英)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THISDOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIEDWARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO’S PRODUCTS INCLUDING LIABILITY OR WARRANTIESRELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHTOR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO’S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL,LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
標簽：
Stellaris
SRAM
32
KB
上傳時間：
2013-11-22
上傳用戶：lixqiang
-
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability.
標簽：
Assembly
Language
C6000
320C
上傳時間：
2013-11-12
上傳用戶：chens000
-
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
標簽：
3.3
看門狗
芯片
上傳時間：
2013-10-22
上傳用戶：taiyang250072
-
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability
標簽：
320C
TMS
320
C54
上傳時間：
2013-12-26
上傳用戶：凌云御清風
-
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標簽：
Virtex
FPGA
PCB
設計手冊
上傳時間：
2014-01-13
上傳用戶：竺羽翎2222
-
The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. As the interfaces get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
標簽：
Virtex
247
WP
高級封裝
上傳時間：
2013-10-22
上傳用戶：1234xhb
-
According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward
標簽：
Xilinx
196
WP
平面顯示器
上傳時間：
2013-10-18
上傳用戶：日光微瀾
-
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
標簽：
CPLD
FPGA
上傳時間：
2013-10-29
上傳用戶：lixqiang
-
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you
solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,
distribute, republish, download, display, post, or transmit the Documentation in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.
Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx
assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections
or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be
provided to you in connection with the Information.
標簽：
CPLD
上傳時間：
2013-10-22
上傳用戶：李哈哈哈
-
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
標簽：
Wire
總線
主機
上傳時間：
2014-12-22
上傳用戶：xanxuan
