FlexCompress is a high-speed compression LIBRARY developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption algorithms that allows you to integrate archiving or backup features into your programs in a fast and easy way.
ZipForge is a fast ZIP compression LIBRARY. With this toolkit you can easily add archive functionality to your projects. ZipForge includes our new unique techonology, a transaction system. This innovative solution gives you a fast and easy way of updating archive files providing data integrity like a reliable database system. ZipForge Personal is free for personal use. Any company that uses ZipForge in its projects must order ZipForge Pro.
Free C++ toolkit to facilitate Monte-Carlo simulation. This is a LIBRARY covered under the LGPL. "MCS-libre" stands for "Monte Carlo Simulation - libre". Documentation and examples are provided.
這是一個免費的用于簡化Monte-Carlo模擬的C++工具包。這是一個遵守LGPL協議的庫。"MCS-libre"代表"Monte Carlo Simulation - libre"。提供了文檔和例子。
自適應(Adaptive)神經網絡源程序
The adaptive Neural Network LIBRARY is a collection of blocks that implement several Adaptive Neural Networks featuring
different adaptation algorithms.~..~
There are 11 blocks that implement basically these 5 kinds of neural networks:
1) Adaptive Linear Network (ADALINE)
2) Multilayer Layer Perceptron with Extended Backpropagation algorithm (EBPA)
3) Radial Basis Functions (RBF) Networks
4) RBF Networks with Extended Minimal Resource Allocating algorithm (EMRAN)
5) RBF and Piecewise Linear Networks with Dynamic Cell Structure (DCS) algorithm
A simulink example regarding the approximation of a scalar nonlinear function of 4 variables
包含一下內容:
* An extensible agent
* An SNMP LIBRARY
* tools to request or set information from SNMP agents
* tools to generate and handle SNMP traps
* a version of the unix netstat command using SNMP
* a graphical Perl/Tk/SNMP based mib browser
The GRLIB IP LIBRARY is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The LIBRARY is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
