Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽： Creating Machines Mentor State
上傳時間： 2013-10-08
上傳用戶：wangzhen1990
DC-link Automotive: MKP1849 (Customized)電動汽車電驅直流母線電容（顧客訂制品）MKP1849系列.MKP1849-可集成母線排，大大降低了寄生電感，提高了系統穩定性。
上傳時間： 2013-10-13
上傳用戶：nanfeicui
J-Link V8個人使用經驗寫成的用戶手冊
上傳時間： 2013-10-07
上傳用戶：hulee
教你如何制作一個J-Link V8仿真器！ 已經成功！
上傳時間： 2013-10-15
上傳用戶：truth12
介紹一種人機交互系統的可靠性設計方案。該系統基于Memory-link通信協議，采用了目前流行的基于ARM7架構的S3C44BOX作為主控芯片，通過RS-422實現人機交互通信。結合抗干擾的硬件設計和穩定有效運行的軟件設計方案，實現了在強干擾下穩定可靠的通信。實驗結果表明，本系統抗干擾能力強、運行穩定可靠，在自主開發控制系統的人機交互通信部分具有一定的參考價值。
標簽： Memory-link 協議 人機交互系統 可靠性設計
上傳時間： 2013-11-21
上傳用戶：cknck
J-LINK仿真器詳細教程 flash下載操作等
上傳時間： 2013-11-14
上傳用戶：JamesB
本文主要介紹MDK4.10下，連接ST-Link II的設置方法，給出了所有所需的配置文件。
上傳時間： 2013-11-22
上傳用戶：kang1923
本文論述了狀態機的verilog編碼風格,以及不同編碼風格的優缺點，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標簽： Synthesis Machine Coding Styles
上傳時間： 2013-10-12
上傳用戶：sardinescn
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
標簽： Synplicity Machine Verilog Design
上傳時間： 2013-10-20
上傳用戶：蒼山觀海
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽： Creating Machines Mentor State
上傳時間： 2013-11-02
上傳用戶：xauthu
