1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時(shí)間： 2022-01-09
上傳用戶(hù)：
電學(xué)中的測(cè)量技術(shù)涉及范圍非常廣,電流測(cè)量在電學(xué)計(jì)量中占有非常重要的位置。如何精確地進(jìn)行電流測(cè)量是精密測(cè)量的一大難題。傳統(tǒng)的電流檢測(cè)電路多采用運(yùn)算放大芯片與片外電流檢測(cè)電路相結(jié)合的方式,電路集成度很低,需要較多的接口和資源才能完成對(duì)電路的檢測(cè)。本文把所有電路部分都集成在一塊芯片上,包括檢測(cè)電阻,運(yùn)算放大器電路及模擬轉(zhuǎn)數(shù)字轉(zhuǎn)換電路,從而在電路內(nèi)部可以進(jìn)行電流檢測(cè),使電路更好的集成化。前置電路使用二級(jí)共源共柵結(jié)構(gòu)的運(yùn)算放大器,減小溝道長(zhǎng)度調(diào)制效應(yīng)造成的電流誤差。10位SAR ADC中采用電容驅(qū)動(dòng)能力強(qiáng)的傳輸門(mén)保證了模數(shù)轉(zhuǎn)化器的有效精度。比較器模塊采用再生鎖存器與遲滯比較器作為基礎(chǔ)單元組合解決精密測(cè)量的問(wèn)題。本設(shè)計(jì)可以作為嵌入芯片內(nèi)的一小部分而檢測(cè)芯片中的微小電流1mA~100mA,工作電壓在1.8v左右,電流檢測(cè)精度預(yù)期達(dá)到10uA的需求。The measurement technology in electricity involves a wide range,and current measurement plays a very important position in electrical measurement.How to accurately measure current is a big problem in precision measurement. The traditional current detecting circuit adopts the combination of the operational amplifier chip and theoff-chip current detecting circuit, The circuit integration is very low, and more interfaces and resources are needed tocomplete the circuit detection.This topic integrates all the circuit parts into one chip, including detection resistance, operational amplifier circuit andanalog to digital conversion circuit. Highly integrated circuit makes the external resources on the chip more intensive,so that current detection can be carried out inside the circuit, so that the circuit can be better integrated. Thefront-end circuit of this project uses two-stage cascade operational amplifier and cascade tube to reduce the currenterror caused by channel Length modulation effect. In 10-bit SAR ADC, the transmission gate with strong capacitivedriving ability ensures the effective accuracy of the analog-to-digital converter. Comparator module uses regenerativelatch and hysteresis comparator as basic unit to solve the difficult problem of precision measurement. This topic can beused as a small part of the embedded chip to detect the micro-current in the chip 1 mA~100 mA, the working voltageis about 1.8v, and the current detection accuracy is expected to reach the requirement of 10 uA.
標(biāo)簽： 電流檢測(cè) 電路 運(yùn)算放大器 adc
上傳時(shí)間： 2022-04-03
上傳用戶(hù)：
le flows through MOS channel while Ih flows across PNP transistor Ih= a/(1-a) le, IE-le+lh=1/(1-a)' le Since IGBT has a long base PNP, a is mainly determined by ar si0 2ar= 1/cosh(1/La), La: ambipolar diff Length a-0.5 (typical value)p MOSFET channel current (saturation), le=U"Cox"W(2"Lch)"(Vc-Vth)le Thus, saturated collector current Ic, sat=1/(1-a)"le=-1/(1-a)"UCox"W/(2Lch)"(Vo-Vth)2Also, transconductance gm, gm= 1/(1-a)"u' Cox W/Lch*(Vo-Vth)Turn-On1. Inversion layer is formed when Vge>Vth2. Apply positive collector bias, +Vce3. Electrons flow from N+ emitter to N-drift layer providing the base current for the PNP transistor4. Since J1 is forward blased, hole carriers are injected from the collector (acts as an emitter).5. Injected hole carriers exceed the doping level of N-drift region (conductivity modulation). Turn-Off1. Remove gate bias (discharge gate)2. Cut off electron current (base current, le, of pnp transistor)
標(biāo)簽： igbt
上傳時(shí)間： 2022-06-20
上傳用戶(hù)：wangshoupeng199
1，使用wireshark獲取完整的UDP報(bào)文打開(kāi)wireshark，設(shè)置監(jiān)聽(tīng)網(wǎng)卡后，使用google chrome瀏覽器訪問(wèn)我騰訊微博的i http://p.t.qq.com/welcomeback.php？lv=1#！/ist/qqfriends/5/？pgv_ref-im.perinfo.pe rinfo.icon？ptlang-2052&pgv-ref-im.perinfo.perinfo.icon，抓得的UDP報(bào)文如圖1所示。分析以上的報(bào)文內(nèi)容，UDP作為一種面向無(wú)連接服務(wù)的運(yùn)輸協(xié)議，其報(bào)文格式相當(dāng)簡(jiǎn)單。第一行中，Source port：64318是源端口號(hào)。第二行中，Destination port：53是目的端口號(hào)。第三行中，Length：34表示UDP報(bào)文段的長(zhǎng)度為34字節(jié)。第四行中，Checksum之后的數(shù)表示檢驗(yàn)和。這里0x表示計(jì)算機(jī)中16進(jìn)制數(shù)的開(kāi)始符，其后的4f0e表示16進(jìn)制表示的檢驗(yàn)和，把它們換成二進(jìn)制表示為：0100 1111 0000 1110.從wireshark的抓包數(shù)據(jù)看出，我抓到的UDP協(xié)議多數(shù)被應(yīng)用層的DNS協(xié)議應(yīng)用。當(dāng)一臺(tái)主機(jī)中的DNS應(yīng)用程序想要進(jìn)行一次查詢(xún)時(shí)，它構(gòu)成了一個(gè)DNS查詢(xún)報(bào)文并將其交給UDP，UDP無(wú)須執(zhí)行任何實(shí)體握手過(guò)程，主機(jī)端的UDP為此報(bào)文添加首部字段，并將其發(fā)出。
上傳時(shí)間： 2022-06-20
上傳用戶(hù)：
VITA 46 Highlights Retain standard 6U and 3U form-factors Height, depth, pitch, front panel arrangements, conduction-cooled interfaces, etc.Support standard-Length PMC and XMC modules· Support high-speed serial fabric on the backplane Tyco MultiGig RT2,7-row connector· Support VME and PCI interfaces for legacy compatibility· Provision for optical connectors as option· Support improved logistics Provide support for Line Replaceable Module(LRM) applications with ESD-protected connector Alignment and keying blocks
標(biāo)簽： vita46
上傳時(shí)間： 2022-07-25
上傳用戶(hù)：
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
