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In an increasing trend, telecommunications, networking,audio and instrumentation require low noise power supplies.In particular, there is interest in low noise, lowdropout linear regulators (LDO). These components powernoise-sensitive circuitry, circuitry that contains noisesensitiveelements or both. Additionally, to conserve power,particularly in battery driven apparatus such as cellulartelephones, the regulators must operate with low input-tooutputvoltages.1 Devices presently becoming availablemeet these requirements (see separate section, “A Familyof 20mVRMS Noise, Low Dropout Regulators”).
標簽：
低噪聲
低壓差穩壓器
性能
上傳時間：
2013-10-30
上傳用戶：yeling1919
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Precision, Low Noise, CMOS, Rail-to-Rail,
Input/Output Operational Amplifiers
Data Sheet AD8605/AD8606/AD8608The AD8605, AD8606, and AD86081 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim? trimming technique, which achieves
標簽：
運算放大器
上傳時間：
2022-02-02
上傳用戶：
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The PW5410B is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 1.8V to 5V input with up to 100mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410B ideally suited for small, battery-powered applications
標簽：
pw5410
上傳時間：
2022-02-11
上傳用戶：wangshoupeng199
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The PW5410A is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 2.7V to 5V input with up to 250mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410A ideally suited for small, battery-powered applications
標簽：
pw5410
上傳時間：
2022-02-11
上傳用戶：
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The JW? 7805 is a low noise low-dropout (LDO) voltage regulator with enable function that operates from 1.8V to 5.5V. It provides up to 300mA of output current and offers low-power operation in miniaturized packaging. JW7805 supports fixed output voltage 0.9V, 1.0V, 1.05V, 1.1V,1.2V, 1.3V, 1.35V, 1.5V, 1.8V, 1.85V, 2.1V, 2.2V, 2.3V, 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V,3.1V, 3.3V, 3.6V, 4.2V, 4.4V and 5.0V. The features of low quiescent current as low as 6uA and almost zero disable current are ideal for powering the battery equipment. JW7805’s low output noise and high PSRR are also friendly to RF systems.
標簽：
JW7805
上傳時間：
2022-05-06
上傳用戶：slq1234567890
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近年來，隨著個人數據通信的發展，功能強大的便攜式數據終端和多媒體終端得到了廣泛的應用。為了實現用戶在任何時間、任何地點均能實現數據通信的目標，要求傳統的計算機網絡由有線向無線、由固定向移動、由單一業務向多媒體發展，這一要求促進了無線局域網技術的發展。在互聯網高速發展的今天，可以認為無線局域網將成為未來的發展趨勢.本課題采用TSMC 0.18um CMOS工藝實現用于IEEE 802.1la協議的5GHz無線局域網接收機射頻前端集成電路一包括低噪聲放大器（Low-NOISE Amplifier，LNA）和下變頻器電路（Downconverter），低噪聲放大器是射頻接收機前端的主要部分，其作用是在盡可能少引入噪聲的條件下對天線接收到的微弱信號進行放大。下變須器是接收機的重要組成部分，它將低噪聲放大器的輸出射頻信號與本振信號進行混頻，產生中頻信號。論文對射頻前端集成電路的原理進行了分析，比較了不同電路結構的性能，給出了射頻前端集成電路的電路設計、版圖設計、仿真結果和測試方案，仿真結果表明，此次設計的射頻前端集成電路具有低噪聲、低功耗的特點，其它性能也完全滿足設計指標要求
標簽：
無線局域網
接收機
上傳時間：
2022-06-20
上傳用戶：
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RF CMOS Low-Phase-Noise LC Oscillator Through Memory Reduction Tail Transistor
標簽：
Low-Phase-Noise
Oscillator
Transistor
Reduction
上傳時間：
2017-07-21
上傳用戶：66666
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Fast settling-time added to the already conflicting requirements of narrow channel spacing and
low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
標簽：
settling-time
requirements
conflicting
already
上傳時間：
2016-04-14
上傳用戶：liansi
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Image enhancement in frequency domain using Fourier center frequency, Gaussian lowpass filter, Low pass filter, high pass filter. Image restoration using medean filter, weiner filter with noise generator such as Gaussian noise, Salt and Pepper noise
標簽：
frequency
enhancement
Gaussian
Fourier
上傳時間：
2017-08-24
上傳用戶：xinzhch
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ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標簽：
Converter
Defi
ADC
轉換器
上傳時間：
2013-11-12
上傳用戶：pans0ul
