Capturing low-level network data can be hard in Java, but it s certainly not impossible If you want to capture network packets in your Java program, you ll need a little help because no parts of the core Java APIAPI give access to low-level network
標(biāo)簽： impossible Capturing low-level certainly
上傳時(shí)間： 2016-03-05
上傳用戶：yuanyuan123
the FXT library: fast transforms and low level algorithms. The package contains many algorithms for programmers: bit manipulation, fast othogonal transforms, arithmetic and number theory algorithms.
標(biāo)簽： algorithms transforms contains library
上傳時(shí)間： 2014-01-09
上傳用戶：星仔
四種典型環(huán)境的cost 207模型的matlab仿真信道代碼
上傳時(shí)間： 2013-12-16
上傳用戶：hongmo
lpc源代碼verilog實(shí)現(xiàn)的。操作low pin count設(shè)備
標(biāo)簽： verilog count lpc low
上傳時(shí)間： 2013-12-20
上傳用戶：稀世之寶039
Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
標(biāo)簽： settling-time requirements conflicting already
上傳時(shí)間： 2016-04-14
上傳用戶：liansi
njg1130 GPS LOW NOISE AMPLIFIER GaAs MMIC
標(biāo)簽： AMPLIFIER NOISE 1130 GaAs
上傳時(shí)間： 2013-12-13
上傳用戶：huangld
COST207.m... ..COST模型 GWSSUS.m.........高斯白噪聲 信道模型的ppt
上傳時(shí)間： 2013-12-21
上傳用戶：Altman
A collection of LDPC(Low-Density Parity-Codes) tools. Including: Code construction Density Evolution Decoding Algorithm Girth average Counter Stopping set and error Floor,etc
標(biāo)簽： Parity-Codes construction Low-Density collection
上傳時(shí)間： 2016-05-10
上傳用戶：liglechongchong
Low Power Circuit Design. hope you can get a lot from it.
標(biāo)簽： Circuit Design Power hope
上傳時(shí)間： 2013-12-16
上傳用戶：fxf126@126.com
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
標(biāo)簽： microcontroller implementation asynchronous low-power
上傳時(shí)間： 2016-06-07
上傳用戶：冇尾飛鉈
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