16位A/D轉換程序，使用MAX+PLUS2做的，用狀態機做的，但不夠完善，望大家見諒
上傳時間： 2016-07-23
上傳用戶：趙云興
The task of clustering Web sessions is to group Web sessions based on similarity and consists of maximizing the intra- group similarity while minimizing the inter-group similarity． The first and foremost question needed to be considered in clustering W b sessions is how to measure the similarity between Web sessions．However．there are many shortcomings in traditiona1 measurements．This paper introduces a new method for measuring similarities between Web pages that takes into account not only the URL but also the viewing time of the visited web page．Yhen we give a new method to measure the similarity of Web sessions using sequence alignment and the similarity of W eb page access in detail Experiments have proved that our method is valid and e幣cient．
標簽： sessions clustering similarity Web
上傳時間： 2014-01-11
上傳用戶：songrui
中山大學編譯原理課程的一個實驗，根據OPP(算符優先)做的一個表達式計算器。 內有實驗的設計文檔。 實驗要求支持sin,cos,max,min,power,mod,boolean,?:,等運算。 這個代碼可以為學習編譯原理的同學參考。
上傳時間： 2014-01-27
上傳用戶：PresidentHuang
用prim算法實驗最小生成樹 本程序中用到函數adjg( )，此函數作用是通過接受輸入的點數和邊數，建立無向圖。函數prg( )用于計算并輸出無向圖的鄰接矩陣。函數prim( )則用PRIM算法來尋找無向圖的最小生成樹 定義了兩個數組lowcost[max],closest[max]，若頂點k加入U中，則令lowcost[k]=0。 定義二維數組g[ ][ ]來建立無向圖的鄰接矩陣。
上傳時間： 2016-10-07
上傳用戶：tonyshao
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標簽： Description Behavorial wb_master Filename
上傳時間： 2014-07-11
上傳用戶：zhanditian
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標簽： bus bidirectional primarily designed
上傳時間： 2013-12-11
上傳用戶：jeffery
采用Altera公司的FPGA芯片，在MAX+plus II軟件平臺上實現多路HDLC電路
上傳時間： 2016-11-13
上傳用戶：zhyiroy
設計一個能進行時、分、秒計時的十二小時制或二十四小時制的數字鐘，并具有定時與鬧鐘功能，能在設定的時間發出鬧鈴音，能非常方便地對小時、分鐘和秒進行手動調節以校準時間，每逢整點，產生報時音報時。 實驗平臺： 1. 一臺PC機； 2. MAX+PLUSII10.1。 Verilog HDL語言實現,還有完整的實驗報告
上傳時間： 2013-12-09
上傳用戶：hphh
這是我用Delphi和Matlab寫的一個程序，可以生成立體圖像（3DS Max 腳本）、將平面圖像立體化、基本矩陣計算、極線校正。作者保留所有權利。請勿用于商業用途。歡迎大家對它進行完善。
上傳時間： 2016-11-27
上傳用戶：dapangxie
function [U,center,result,w,obj_fcn]= fenlei(data) [data_n,in_n] = size(data) m= 2 ％ Exponent for U max_iter = 100 ％ Max. iteration min_impro =1e-5 ％ Min. improvement c=3 [center, U, obj_fcn] = fcm(data, c) for i=1:max_iter if F(U)>0.98 break else w_new=eye(in_n,in_n) center1=sum(center)/c a=center1(1)./center1 deta=center-center1(ones(c,1),:) w=sqrt(sum(deta.^2)).*a for j=1:in_n w_new(j,j)=w(j) end data1=data*w_new [center, U, obj_fcn] = fcm(data1, c) center=center./w(ones(c,1),:) obj_fcn=obj_fcn/sum(w.^2) end end display(i) result=zeros(1,data_n) U_=max(U) for i=1:data_n for j=1:c if U(j,i)==U_(i) result(i)=j continue end end end
標簽： data function Exponent obj_fcn
上傳時間： 2013-12-18
上傳用戶：ynzfm
