溫濕度傳感器 sht11 仿真程序 sbit out =P3^0; //加熱口 //sbit input =P1^1;//檢測(cè)口 //sbit speek =P2^0;//報(bào)警 sbit clo =P3^7;//時(shí)鐘 sbit ST =P3^5;//開始 sbit EOC =P3^6;//成功信號(hào) sbit gwei =P3^4;//個(gè)位 sbit swei =P3^3;//十位 sbit bwei =P3^2;//百位 sbit qwei =P3^1;//千位 sbit speak =P0^0;//報(bào)警音 sbit bjled =P0^1;//報(bào)警燈 sbit zcled =P0^2;//正常LED int count; uchar xianzhi;//取轉(zhuǎn)換結(jié)果 uchar seth;//高時(shí)間 uchar setl;//低時(shí)間 uchar seth_mi;//高時(shí)間 uchar setl_mi;//低時(shí)間 bit hlbz;//高低標(biāo)志 bit clbz; bit spbz; ///定時(shí)中斷程序/// void t0 (void) interrupt 1 using 0 { TH0=(65536-200)/256;//5ms*200=1000ms=1s TL0=(65536-200)%256; clo=!clo;//產(chǎn)生時(shí)鐘 if(count>5000) { if(hlbz) { if(seth_mi==0){seth_mi=seth;hlbz=0;out=0;} else seth_mi--; } if(!hlbz) { if(setl_mi==0){setl_mi=setl;hlbz=1;out=1;} else setl_mi--; } count=0; } else count++; } ///////////// ///////延時(shí)/////// delay(int i) { while(--i); } ///////顯示處理/////// xianshi() { int abcd=0; int i; for (i=0;i<5;i++) { abcd=xianzhi; gwei=1; swei=1; bwei=1; qwei=1; P1=dispcode[abcd/1000]; qwei=0; delay(70); qwei=1; abcd=abcd%1000; P1=dispcode[abcd/100]; bwei=0; delay(70); bwei=1; abcd=abcd%100; P1=dispcode[abcd/10]; swei=0; delay(70); swei=1; abcd=abcd%10; P1=dispcode[abcd]; gwei=0; delay(70); gwei=1; } } doing() { if(xianzhi>100) {bjled=0;speak=1;zcled=1;} else {bjled=1;speak=0;zcled=0;} } void main(void) { seth=60;//h60秒 setl=90;//l90秒 seth_mi=60;//h60秒 setl_mi=90;//l90秒 TMOD=0X01;//定時(shí)0 16位工作模式 TH0=(65536-200)/256; TL0=(65536-200)%256; TR0=1; //開始計(jì)時(shí) ET0=1; //開定時(shí)0中斷 EA=1; //開全中斷 while(1) { ST=0; _nop_(); ST=1; _nop_(); ST=0; // EOC=0; xianshi(); while(!EOC) { xianshi(); } xianzhi=P2; xianshi(); doing(); } }
上傳時(shí)間： 2013-11-07
上傳用戶：我們的船長(zhǎng)
超聲波傳感器適用于對(duì)大幅的平面進(jìn)行靜止測(cè)距。普通的超聲波傳感器測(cè)距范圍大概是 2cm~450cm，分辨率3mm（淘寶賣家說的，筆者測(cè)試環(huán)境沒那么好，個(gè)人實(shí)測(cè)比較穩(wěn)定的 距離10cm~2m 左右，超過此距離就經(jīng)常有偶然不準(zhǔn)確的情況發(fā)生了，當(dāng)然不排除筆者技術(shù) 問題。） 測(cè)試對(duì)象是淘寶上面最便宜的SRF-04 超聲波傳感器，有四個(gè)腳：5v 電源腳（Vcc），觸發(fā)控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超聲波傳感器參數(shù)比較 模塊工作原理： 采用IO 觸發(fā)測(cè)距，給至少10us 的高電平信號(hào)； 模塊自動(dòng)發(fā)送8個(gè)40KHz 的方波，自動(dòng)檢測(cè)是否有信號(hào)返回； 有信號(hào)返回，通過IO 輸出一高電平，高電平持續(xù)的時(shí)間就是超聲波從發(fā)射到返回的時(shí)間．測(cè)試距離=(高電平時(shí)間*聲速(340m/s))/2; 電路連接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低電平發(fā)一個(gè)短時(shí)間脈沖去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //將回波時(shí)間換算成cm cm = (int(cm * 100.0)) / 100.0; //保留兩位小數(shù) Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }
上傳時(shí)間： 2013-10-18
上傳用戶：星仔
MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評(píng)估板 軟件
上傳時(shí)間： 2013-11-23
上傳用戶：truth12
怎樣使用Nios II處理器來構(gòu)建多處理器系統(tǒng) Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上傳時(shí)間： 2013-11-21
上傳用戶：lo25643
protel 99se 使用技巧以及常見問題解決方法：里面有一些protel 99se 特別技巧，還有我們經(jīng)常遇到的一些問題！如何使一條走線至兩個(gè)不同位置零件的距離相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的規(guī)則中來新增規(guī)則設(shè)定,最后再用Tools/EqualizeNet Lengths 來等長(zhǎng)化即可。 Q02、在SCHLIB中造一零件其PIN的屬性，如何決定是Passive, Input, I/O, Hi- Z,Power,…..？在HELP中能找到說明嗎？市面有關(guān) SIM？PLD？的書嗎？或貴公司有講義？ 你可在零件庫(kù)自制零件時(shí)點(diǎn)選零件Pin腳,并在Electrical Type里,可以自行設(shè)定PIN的 屬性,您可參考臺(tái)科大的Protel sch 99se 里面有介紹關(guān)于SIM的內(nèi)容。 Q03、請(qǐng)問各位業(yè)界前輩,如何能順利讀取pcad8.6版的線路圖,煩請(qǐng)告知 Protel 99SE只能讀取P-CAD 2000的ASCII檔案格式,所以你必須先將P-CAD8.6版的格式轉(zhuǎn)為P-CAD 2000的檔案格式,才能讓Protel讀取。 Q04、請(qǐng)問我該如何標(biāo)示線徑大小的那個(gè)平方呢 你可以將格點(diǎn)大小設(shè)小,還有將字形大小縮小,再放置數(shù)字的平方位置即可。 Q05、請(qǐng)問我一次如何更改所有組件的字型 您可以點(diǎn)選其中一個(gè)組件字型,再用Global的方法就可以達(dá)成你的要求。
上傳時(shí)間： 2015-01-01
上傳用戶：yxgi5
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時(shí)間： 2013-11-10
上傳用戶：yy_cn
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時(shí)間： 2013-12-14
上傳用戶：逗逗666
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
標(biāo)簽： allegro manual cx 教程
上傳時(shí)間： 2015-01-02
上傳用戶：zhangyi99104144
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
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