The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
標(biāo)簽： Infra-red Remote Cont 05K
上傳時(shí)間： 2014-01-24
上傳用戶(hù)：zl5712176
AVR高速嵌入式單片機(jī)原理與應(yīng)用(修訂版)詳細(xì)介紹ATMEL公司開(kāi)發(fā)的AVR高速嵌入式單片機(jī)的結(jié)構(gòu)；講述AVR單片機(jī)的開(kāi)發(fā)工具和集成開(kāi)發(fā)環(huán)境（IDE）,包括Studio調(diào)試工具、AVR單片機(jī)匯編器和單片機(jī)串行下載編程；學(xué)習(xí)指令系統(tǒng)時(shí),每條指令均有實(shí)例,邊學(xué)習(xí)邊調(diào)試,使學(xué)習(xí)者看得見(jiàn)指令流向及操作結(jié)果,真正理解每條指令的功能及使用注意事項(xiàng)；介紹AVR系列多種單片機(jī)功能特點(diǎn)、實(shí)用程序設(shè)計(jì)及應(yīng)用實(shí)例；作為提高篇,講述簡(jiǎn)單易學(xué)、適用AVR單片機(jī)的高級(jí)語(yǔ)言BASCOMAVR及ICC AVR C編譯器。 AVR高速嵌入式單片機(jī)原理與應(yīng)用(修訂版) 目錄 第一章ATMEL單片機(jī)簡(jiǎn)介1.1ATMEL公司產(chǎn)品的特點(diǎn)11.2AT90系列單片機(jī)簡(jiǎn)介21.3AT91M系列單片機(jī)簡(jiǎn)介2第二章AVR單片機(jī)系統(tǒng)結(jié)構(gòu)2.1AVR單片機(jī)總體結(jié)構(gòu)42.2AVR單片機(jī)中央處理器CPU62.2.1結(jié)構(gòu)概述72.2.2通用寄存器堆92.2.3X、Y、Z寄存器92.2.4ALU運(yùn)算邏輯單元92.3AVR單片機(jī)存儲(chǔ)器組織102.3.1可下載的Flash程序存儲(chǔ)器102.3.2內(nèi)部和外部的SRAM數(shù)據(jù)存儲(chǔ)器102.3.3EEPROM數(shù)據(jù)存儲(chǔ)器112.3.4存儲(chǔ)器訪問(wèn)和指令執(zhí)行時(shí)序112.3.5I/O存儲(chǔ)器132.4AVR單片機(jī)系統(tǒng)復(fù)位162.4.1復(fù)位源172.4.2加電復(fù)位182.4.3外部復(fù)位192.4.4看門(mén)狗復(fù)位192.5AVR單片機(jī)中斷系統(tǒng)202.5.1中斷處理202.5.2外部中斷232.5.3中斷應(yīng)答時(shí)間232.5.4MCU控制寄存器 MCUCR232.6AVR單片機(jī)的省電方式242.6.1休眠狀態(tài)242.6.2空閑模式242.6.3掉電模式252.7AVR單片機(jī)定時(shí)器／計(jì)數(shù)器252.7.1定時(shí)器／計(jì)數(shù)器預(yù)定比例器252.7.28位定時(shí)器／計(jì)數(shù)器0252.7.316位定時(shí)器／計(jì)數(shù)器1272.7.4看門(mén)狗定時(shí)器332.8AVR單片機(jī)EEPROM讀／寫(xiě)訪問(wèn)342.9AVR單片機(jī)串行接口352.9.1同步串行接口 SPI352.9.2通用串行接口 UART402.10AVR單片機(jī)模擬比較器452.10.1模擬比較器452.10.2模擬比較器控制和狀態(tài)寄存器ACSR462．11AVR單片機(jī)I/O端口472.11.1端口A472.11.2端口 B482.11.3端口 C542.11.4端口 D552.12AVR單片機(jī)存儲(chǔ)器編程612.12.1編程存儲(chǔ)器鎖定位612.12.2熔斷位612.12.3芯片代碼612.12.4編程 Flash和 EEPROM612.12.5并行編程622.12．6串行下載662.12.7可編程特性67第三章AVR單片機(jī)開(kāi)發(fā)工具3.1AVR實(shí)時(shí)在線仿真器ICE200693.2JTAG ICE仿真器693.3AVR嵌入式單片機(jī)開(kāi)發(fā)下載實(shí)驗(yàn)器SL?AVR703.4AVR集成開(kāi)發(fā)環(huán)境(IDE)753.4.1AVR Assembler編譯器753.4.2AVR Studio773.4.3AVR Prog783.5SL?AVR系列組態(tài)開(kāi)發(fā)實(shí)驗(yàn)系統(tǒng)793.6SL?AVR*.ASM源文件說(shuō)明81第四章AVR單片機(jī)指令系統(tǒng)4.1指令格式844.1.1匯編指令844.1.2匯編器偽指令844.1.3表達(dá)式874.2尋址方式894.3數(shù)據(jù)操作和指令類(lèi)型924.3.1數(shù)據(jù)操作924.3.2指令類(lèi)型924.3.3指令集名詞924.4算術(shù)和邏輯指令934.4.1加法指令934.4.2減法指令974.4.3乘法指令1014.4.4取反碼指令1014.4.5取補(bǔ)指令1024.4.6比較指令1034.4.7邏輯與指令1054.4.8邏輯或指令1074.4.9邏輯異或指令1104.5轉(zhuǎn)移指令1114.5.1無(wú)條件轉(zhuǎn)移指令1114.5.2條件轉(zhuǎn)移指令1144.6數(shù)據(jù)傳送指令1354.6.1直接數(shù)據(jù)傳送指令1354.6.2間接數(shù)據(jù)傳送指令1374.6.3從程序存儲(chǔ)器直接取數(shù)據(jù)指令1444.6.4I／O口數(shù)據(jù)傳送指令1454.6.5堆棧操作指令1464.7位指令和位測(cè)試指令1474.7.1帶進(jìn)位邏輯操作指令1474.7.2位變量傳送指令1514.7.3位變量修改指令1524.7.4其它指令1614.8新增指令（新器件）1624.8.1EICALL-- 延長(zhǎng)間接調(diào)用子程序1624.8.2EIJMP--擴(kuò)展間接跳轉(zhuǎn)1634.8.3ELPM--擴(kuò)展裝載程序存儲(chǔ)器1644.8.4ESPM--擴(kuò)展存儲(chǔ)程序存儲(chǔ)器1644.8.5FMUL--小數(shù)乘法1664.8.6FMULS--有符號(hào)數(shù)乘法1664.8.7FMULSU--有符號(hào)小數(shù)和無(wú)符號(hào)小數(shù)乘法1674.8.8MOVW--拷貝寄存器字1684.8.9MULS--有符號(hào)數(shù)乘法1694.8.10MULSU--有符號(hào)數(shù)與無(wú)符號(hào)數(shù)乘法1694.8.11SPM--存儲(chǔ)程序存儲(chǔ)器170 第五章AVR單片機(jī)AT90系列5.1AT90S12001725.1.1特點(diǎn)1725.1.2描述1735.1.3引腳配置1745.1.4結(jié)構(gòu)縱覽1755.2AT90S23131835.2.1特點(diǎn)1835.2.2描述1845.2.3引腳配置1855.3ATmega8/8L1855.3.1特點(diǎn)1865.3.2描述1875.3.3引腳配置1895.3.4開(kāi)發(fā)實(shí)驗(yàn)工具1905.4AT90S2333/44331915.4.1特點(diǎn)1915.4.2描述1925.4.3引腳配置1945.5AT90S4414/85151955.5.1特點(diǎn)1955.5.2AT90S4414和AT90S8515的比較1965.5.3引腳配置1965.6AT90S4434/85351975.6.1特點(diǎn)1975.6.2描述1985.6.3AT90S4434和AT90S8535的比較1985.6.4引腳配置2005.6.5AVR RISC結(jié)構(gòu)2015.6.6定時(shí)器/計(jì)數(shù)器2125.6.7看門(mén)狗定時(shí)器 2175.6.8EEPROM讀/寫(xiě)2175.6.9串行外設(shè)接口SPI2175.6.10通用串行接口UART2175.6.11模擬比較器 2175.6.12模數(shù)轉(zhuǎn)換器2185.6.13I/O端口2235.7ATmega83/1632285.7.1特點(diǎn)2285.7.2描述2295.7.3ATmega83與ATmega163的比較2315.7.4引腳配置2315.8ATtiny10/11/122325.8.1特點(diǎn)2325.8.2描述2335.8.3引腳配置2355.9ATtiny15/L2375.9.1特點(diǎn)2375.9.2描述2375.9.3引腳配置2395 .10ATmega128/128L2395.10.1特點(diǎn)2405.10.2描述2415.10.3引腳配置2435.10.4開(kāi)發(fā)實(shí)驗(yàn)工具2455.11ATmega1612465.11.1特點(diǎn)2465.11.2描述2475.11.3引腳配置2475.12AVR單片機(jī)替代MCS51單片機(jī)249第六章實(shí)用程序設(shè)計(jì)6．1程序設(shè)計(jì)方法2506.1.1程序設(shè)計(jì)步驟2506．1．2程序設(shè)計(jì)技術(shù)2506.2應(yīng)用程序舉例2516.2.1內(nèi)部寄存器和位定義文件2516.2.2訪問(wèn)內(nèi)部 EEPROM2546.2.3數(shù)據(jù)塊傳送2546.2.4乘法和除法運(yùn)算應(yīng)用一2556.2.5乘法和除法運(yùn)算應(yīng)用二2556.2.616位運(yùn)算2556.2.7BCD運(yùn)算2556.2.8冒泡分類(lèi)算法2556.2.9設(shè)置和使用模擬比較器2556.2.10半雙工中斷方式UART應(yīng)用一2556.2.11半雙工中斷方式UART應(yīng)用二2566.2.128位精度A／D轉(zhuǎn)換器2566.2.13裝載程序存儲(chǔ)器2566.2.14安裝和使用相同模擬比較器2566.2.15CRC程序存儲(chǔ)的檢查2566.2.164×4鍵區(qū)休眠觸發(fā)方式2576.2.17多工法驅(qū)動(dòng)LED和4×4鍵區(qū)掃描2576.2.18I2C總線2576.2.19I2C工作2586.2.20SPI軟件2586.2.21驗(yàn)證SLAVR實(shí)驗(yàn)器及AT90S1200的口功能12596.2.22驗(yàn)證SLAVR實(shí)驗(yàn)器及AT90S1200的口功能22596.2.23驗(yàn)證SLAVR實(shí)驗(yàn)器及具有DIP40封裝的口功能第七章AVR單片機(jī)的應(yīng)用7.1通用延時(shí)子程序2607.2簡(jiǎn)單I/O口輸出實(shí)驗(yàn)2667.2.1SLAVR721.ASM 2667.2.2SLAVR722.ASM2677.2.3SLAVR723.ASM2687.2.4SLAVR724.ASM2707.2.5SLAVR725.ASM2717.2.6SLAVR726.ASM2727.2.7SLAVR727.ASM2737.3綜合程序2747.3.1LED/LCD/鍵盤(pán)掃描綜合程序2747.3.2LED鍵盤(pán)掃描綜合程序2757.3.3在LED上實(shí)現(xiàn)字符8的循環(huán)移位顯示程序2757.3.4電腦放音機(jī)2777.3.5鍵盤(pán)掃描程序2857.3.6十進(jìn)制計(jì)數(shù)顯示2867.3.7廉價(jià)的A/D轉(zhuǎn)換器2897.3.8高精度廉價(jià)的A/D轉(zhuǎn)換器2947.3.9星星燈2977.3.10按鈕猜數(shù)程序2987.3.11漢字的輸入3047.4復(fù)雜實(shí)用程序3067.4.110位A/D轉(zhuǎn)換3067.4.2步進(jìn)電機(jī)控制程序3097.4.3測(cè)脈沖寬度3127.4.4LCD顯示8字循環(huán)3187.4.5LED電腦時(shí)鐘3247.4.6測(cè)頻率3307.4.7測(cè)轉(zhuǎn)速3327.4.8AT90S8535的A/D轉(zhuǎn)換334第八章BASCOMAVR的應(yīng)用8.1基于高級(jí)語(yǔ)言BASCOMAVR的單片機(jī)開(kāi)發(fā)平臺(tái)3408.2BASCOMAVR軟件平臺(tái)的安裝與使用3418.3AVR I/O口的應(yīng)用3458.3.1LED發(fā)光二極管的控制3458.3.2簡(jiǎn)易手控廣告燈3468.3.3簡(jiǎn)易電腦音樂(lè)放音機(jī)3478.4LCD顯示器3498.4.1標(biāo)準(zhǔn)LCD顯示器的應(yīng)用3498.4.2簡(jiǎn)單游戲機(jī)--按鈕猜數(shù)3518.5串口通信UART3528.5.1AVR系統(tǒng)與PC的簡(jiǎn)易通信3538.5.2PC控制的簡(jiǎn)易廣告燈3548.6單總線接口和溫度計(jì)3568.7I2C總線接口和簡(jiǎn)易IC卡讀寫(xiě)器359第九章ICC AVR C編譯器的使用9.1ICC AVR的概述3659.1.1介紹ImageCraft的ICC AVR3659.1.2ICC AVR中的文件類(lèi)型及其擴(kuò)展名3659.1.3附注和擴(kuò)充3669.2ImageCraft的ICC AVR編譯器安裝3679.2.1安裝SETUP.EXE程序3679.2.2對(duì)安裝完成的軟件進(jìn)行注冊(cè)3679.3ICC AVR導(dǎo)游3689.3.1起步3689.3.2C程序的剖析3699.4ICC AVR的IDE環(huán)境3709.4.1編譯一個(gè)單獨(dú)的文件3709.4.2創(chuàng)建一個(gè)新的工程3709.4.3工程管理3719.4.4編輯窗口3719.4.5應(yīng)用構(gòu)筑向?qū)?719.4.6狀態(tài)窗口3719.4.7終端仿真3719.5C庫(kù)函數(shù)與啟動(dòng)文件3729.5.1啟動(dòng)文件3729.5.2常用庫(kù)函數(shù)3729.5.3字符類(lèi)型庫(kù)3739.5.4浮點(diǎn)運(yùn)算庫(kù)3749.5.5標(biāo)準(zhǔn)輸入/輸出庫(kù)3759.5.6標(biāo)準(zhǔn)庫(kù)和內(nèi)存分配函數(shù)3769.5.7字符串函數(shù)3779.5.8變量參數(shù)函數(shù)3799.5.9堆棧檢查函數(shù)3799.6AVR硬件訪問(wèn)的編程3809.6.1訪問(wèn)AVR的底層硬件3809.6.2位操作3809.6.3程序存儲(chǔ)器和常量數(shù)據(jù)3819.6.4字符串3829.6.5堆棧3839.6.6在線匯編3839.6.7I/O寄存器3849.6.8絕對(duì)內(nèi)存地址3849.6.9C任務(wù)3859.6.10中斷操作3869.6.11訪問(wèn)UART3879.6.12訪問(wèn)EEPROM3879.6.13訪問(wèn)SPI3889.6.14相對(duì)轉(zhuǎn)移/調(diào)用的地址范圍3889.6.15C的運(yùn)行結(jié)構(gòu)3889.6.16匯編界面和調(diào)用規(guī)則3899.6.17函數(shù)返回非整型值3909.6.18程序和數(shù)據(jù)區(qū)的使用3909.6.19編程區(qū)域3919.6.20調(diào)試3919.7應(yīng)用舉例*3929.7.1讀/寫(xiě)口3929.7.2延時(shí)函數(shù)3929.7.3讀/寫(xiě)EEPROM3929.7.4AVR的PB口變速移位3939.7.5音符聲程序3939.7.68字循環(huán)移位顯示程序3949.7.7鋸齒波程序3959.7.8正三角波程序3969.7.9梯形波程序396附錄1AT89系列單片機(jī)簡(jiǎn)介398附錄2AT94K系列現(xiàn)場(chǎng)可編程系統(tǒng)標(biāo)準(zhǔn)集成電路401附錄3指令集綜合404附錄4AVR單片機(jī)選型表408參 考 文 獻(xiàn)412
上傳時(shí)間： 2013-11-08
上傳用戶(hù)：xcy122677
基于單片機(jī)的汽車(chē)多功能報(bào)警系統(tǒng)設(shè)計(jì)The Design of Automobile Multi-function AlarmingBased on Single Chip Computer劉法治趙明富寧睡達(dá)(河 南 科 技 學(xué) 院 ，新 鄉(xiāng) 453 00 3)摘要介紹了一種基于單片機(jī)控制的汽車(chē)多功能報(bào)警系統(tǒng)，它能對(duì)汽車(chē)的潤(rùn)滑系統(tǒng)油壓、制動(dòng)系統(tǒng)氣壓、冷卻系統(tǒng)溫度、輪胎欠壓及防盜進(jìn)行自動(dòng)檢測(cè)，并在發(fā)現(xiàn)異常情況時(shí)，發(fā)出聲光報(bào)警。闡述了該報(bào)警系統(tǒng)的硬件組成及軟件設(shè)計(jì)方法。關(guān)鍵詞單片機(jī)傳感器數(shù)模轉(zhuǎn)換報(bào)警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly場(chǎng)thesystem. Audio and visual alarms wil be provided under abnormal conditions廠The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽車(chē)多功能報(bào)苦器硬件系統(tǒng)設(shè)計(jì)根據(jù) 系 統(tǒng) 實(shí)際需要和產(chǎn)品性?xún)r(jià)比，選用ATMEL公司新生產(chǎn)的采用CMOs工藝的低功耗、高性能8位單片機(jī)AT89S52作為系統(tǒng)的控制器。AT89S52的片內(nèi)有8k Bytes LSP Flash閃爍存儲(chǔ)器，可進(jìn)行100(〕次寫(xiě)、擦除操作;256Bytes內(nèi)部數(shù)據(jù)存儲(chǔ)器(RAM);3 2 根可編程輸N輸出線;2個(gè)可編程全雙工串行通道;看門(mén)狗(WTD)電路等。系統(tǒng)由傳感器、單片機(jī)、模數(shù)轉(zhuǎn)換器、無(wú)線信號(hào)發(fā)射電路、指示燈驅(qū)動(dòng)電路、聲光報(bào)警驅(qū)動(dòng)電KD一9563，發(fā)出三聲二閃光。并觸發(fā)一個(gè)高電平，驅(qū)動(dòng)無(wú)線信號(hào)發(fā)射電路。
標(biāo)簽： 單片機(jī) 汽車(chē) 多功能 報(bào)警
上傳時(shí)間： 2013-11-09
上傳用戶(hù)：gxmm
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶(hù)：瓦力瓦力hong
為提升虛擬儀器傳輸速率與實(shí)時(shí)性能，擴(kuò)展監(jiān)測(cè)范圍，在VC的軟件平臺(tái)上設(shè)計(jì)了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比，該系統(tǒng)采用嵌入式系統(tǒng)完成信號(hào)采集，采用工業(yè)以太網(wǎng)為傳輸介質(zhì)，通過(guò)線性插值算法和多線程編程思想，實(shí)現(xiàn)波形顯示、參數(shù)計(jì)算、頻譜分析以及波形存儲(chǔ)及回放功能。實(shí)驗(yàn)結(jié)果表明，該虛擬示波器可以實(shí)現(xiàn)20 kHz采樣頻率下的波形精確顯示，達(dá)到預(yù)期的各項(xiàng)指標(biāo)。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
標(biāo)簽： 以太網(wǎng) 虛擬 波器設(shè)計(jì)
上傳時(shí)間： 2013-11-25
上傳用戶(hù)：wbwyl
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過(guò)同步字頭攜帶相關(guān)碼的方法來(lái)實(shí)現(xiàn)同步，但對(duì)于快跳頻來(lái)說(shuō)，由于是一跳或者多跳傳輸一個(gè)調(diào)制符號(hào)，難以攜帶相關(guān)碼。對(duì)此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時(shí)間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：mpquest
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶(hù)：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽： 時(shí)鐘恢復(fù) 英文
上傳時(shí)間： 2013-10-30
上傳用戶(hù)：ysjing
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶(hù)：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時(shí)間： 2013-11-10
上傳用戶(hù)：yy_cn
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