The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: This article explains the recent trend in heart-rate and fitness monitors to go wireless toeliminate cables to allow free movement, and allow convenient data collection without the need to plug intheir devices. It details a typical wireless system, using the MAX1472 crystal-referenced phase-lockedloop (PLL) VHF/UHF transmitter.
標簽： Heart-RateFitness Monitors Wireless Go
上傳時間： 2013-11-11
上傳用戶：xiaowei314
為滿足無線網絡技術具有低功耗、節點體積小、網絡容量大、網絡傳輸可靠等技術要求，設計了一種以MSP430單片機和CC2420射頻收發器組成的無線傳感節點。通過分析其節點組成，提出了ZigBee技術中的幾種網絡拓撲形式，并研究了ZigBee路由算法。針對不同的傳輸要求形式選用不同的網絡拓撲形式可以盡大可能地減少系統成本。同時針對不同網絡選用正確的ZigBee路由算法有效地減少了網絡能量消耗，提高了系統的可靠性。應用試驗表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統的有線通信方式相比可以節約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
上傳時間： 2013-10-09
上傳用戶：robter
同步技術是跳頻通信系統的關鍵技術之一，尤其是在快速跳頻通信系統中，常規跳頻通信通過同步字頭攜帶相關碼的方法來實現同步，但對于快跳頻來說，由于是一跳或者多跳傳輸一個調制符號，難以攜帶相關碼。對此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關碼的困難。分析了同步性能，仿真結果表明該方案同步時間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上傳時間： 2013-11-23
上傳用戶：mpquest
The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上傳時間： 2014-01-04
上傳用戶：LANCE
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
上傳時間： 2013-10-30
上傳用戶：ysjing
ARM通訊 H-JTAG 是一款簡單易用的的調試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實現調試代理的功能，而H-FLASHER則實現了FLASH 燒寫的功能。H-JTAG 的基本結構如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調試，并且支持大多數主流的ARM調試軟件，如ADS、RVDS、IAR 和KEIL。通過靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調試小板。同時，附帶的H-FLASHER 燒寫軟件還支持常用片內片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個簡單易用的ARM 調試開發平臺。H-JTAG 的功能和特定總結如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內FLASH 的自動下載；
上傳時間： 2014-12-01
上傳用戶：Miyuki
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時間： 2013-11-10
上傳用戶：yy_cn
