The TW9910 is a Multi-Standard video decoder and encoder chip that is designed for multimedia applications. It uses the mixed-signal 1.8V CMOS technology to provide a low- power integrated solution.
上傳時間： 2013-04-24
上傳用戶：金宜
Wireless communication is witnessing tremendous growth with great proliferation of different standards covering wide ,local and personal area networks
標(biāo)簽： Multi-Standard Receivers Wireless CMOS
上傳時間： 2020-05-31
上傳用戶：shancjb
CDMA Wireless AT Commands. This contains the standard AT commands used by CDMA mobiles and modems. This file is from Multi Tech Systems.
標(biāo)簽： CDMA Wireless Commands contains
上傳時間： 2017-02-12
上傳用戶：rocwangdp
Multi-carrier modulation? Orthogonal Frequency Division Multi- plexing (OFDM) particularly? has been successfully applied to a wide variety of digital communications applications over the past several years. Although OFDM has been chosen as the physical layer standard for a diversity of important systems? the theory? algorithms? and implementation techniques remain subjects of current interest. This is clear from the high volume of papers appearing in technical journals and conferences.
標(biāo)簽： COMMUNICATIONS MULTI-CARRIER DIGITAL
上傳時間： 2020-05-31
上傳用戶：shancjb
·IEEE Std 1364-2001 Standard Verilog hardware description language
標(biāo)簽： nbsp description Standard hardware
上傳時間： 2013-06-20
上傳用戶：蟲蟲蟲蟲蟲蟲
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Embedded C Coding Standard 嵌入式標(biāo)準(zhǔn)C
標(biāo)簽： Embedded Standard Coding
上傳時間： 2013-11-02
上傳用戶：xiaoyuer
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
multi-line Adjunct Communication Server
標(biāo)簽： Communication multi-line Adjunct Server
上傳時間： 2015-01-03
上傳用戶：784533221
多線程 ( Multi-Thread ) RS232 串行口通訊控件 ( 1.82 版，無源碼 Delphi 3.0/4.0/5.0 版適用 )，作者: Varian Software Services NL。
標(biāo)簽： Multi-Thread 1.82 232 RS
上傳時間： 2013-12-11
上傳用戶：2525775
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