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  • 時(shí)鐘恢復(fù)設(shè)計(jì)_英文版

    Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.

    標(biāo)簽: 時(shí)鐘恢復(fù) 英文

    上傳時(shí)間: 2013-10-30

    上傳用戶:ysjing

  • H-JTAG調(diào)試軟件下載

    ARM通訊   H-JTAG 是一款簡單易用的的調(diào)試代理軟件,功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個(gè)工具軟件:H-JTAG SERVER 和H-FLASHER。其中,H-JTAG SERVER 實(shí)現(xiàn)調(diào)試代理的功能,而H-FLASHER則實(shí)現(xiàn)了FLASH 燒寫的功能。H-JTAG 的基本結(jié)構(gòu)如下圖1-1所示。  H-JTAG支持所有基于ARM7 和ARM9的芯片的調(diào)試,并且支持大多數(shù)主流的ARM調(diào)試軟件,如ADS、RVDS、IAR 和KEIL。通過靈活的接口配置,H-JTAG 可以支持WIGGLER,SDT-JTAG 和用戶自定義的各種JTAG 調(diào)試小板。同時(shí),附帶的H-FLASHER 燒寫軟件還支持常用片內(nèi)片外FLASH 的燒寫。使用H-JTAG,用戶能夠方便的搭建一個(gè)簡單易用的ARM 調(diào)試開發(fā)平臺(tái)。H-JTAG 的功能和特定總結(jié)如下: 1. 支持 RDI 1.5.0 以及 1.5.1; 2. 支持所有ARM7 以及 ARM9 芯片; 3. 支持 THUMB 以及ARM 指令; 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN; 5. 支持 SEMIHOSTING; 6. 支持 WIGGLER, SDT-JTAG和用戶自定義JTAG調(diào)試板; 7. 支持 WINDOWS 9.X/NT/2000/XP; 8.支持常用FLASH 芯片的編程燒寫; 9. 支持LPC2000 和AT91SAM 片內(nèi)FLASH 的自動(dòng)下載;

    標(biāo)簽: H-JTAG 調(diào)試軟件

    上傳時(shí)間: 2014-12-01

    上傳用戶:Miyuki

  • DesignSpark PCB設(shè)計(jì)工具軟件_免費(fèi)下載

    DesignSpark PCB 第3版現(xiàn)已推出! 包括3種全新功能: 1. 模擬介面 Simulation Interface 2. 設(shè)計(jì)計(jì)算機(jī) Design Calculator 3. 零件群組 Component Grouping 第3版新功能介紹 (含資料下載) 另外, 中文版的教學(xué)已經(jīng)準(zhǔn)備好了, 備有簡體和繁體版, 趕快下載來看看! 設(shè)計(jì)PCB產(chǎn)品激活:激活入品 Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum。

    標(biāo)簽: DesignSpark PCB 設(shè)計(jì)工具 免費(fèi)下載

    上傳時(shí)間: 2013-10-19

    上傳用戶:小眼睛LSL

  • DesignSpark PCB設(shè)計(jì)工具軟件_免費(fèi)下載

    DesignSpark PCB 第3版現(xiàn)已推出! 包括3種全新功能: 1. 模擬介面 Simulation Interface 2. 設(shè)計(jì)計(jì)算機(jī) Design Calculator 3. 零件群組 Component Grouping 第3版新功能介紹 (含資料下載) 另外, 中文版的教學(xué)已經(jīng)準(zhǔn)備好了, 備有簡體和繁體版, 趕快下載來看看! 設(shè)計(jì)PCB產(chǎn)品激活:激活入品 Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum。

    標(biāo)簽: DesignSpark PCB 設(shè)計(jì)工具 免費(fèi)下載

    上傳時(shí)間: 2013-10-07

    上傳用戶:a67818601

  • Xilinx UltraScale:新一代架構(gòu)滿足您的新一代架構(gòu)需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標(biāo)簽: UltraScale Xilinx 架構(gòu)

    上傳時(shí)間: 2013-11-21

    上傳用戶:wxqman

  • 使用Nios II軟件構(gòu)建工具

     使用Nios II軟件構(gòu)建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.

    標(biāo)簽: Nios 軟件

    上傳時(shí)間: 2013-10-12

    上傳用戶:china97wan

  • Nios II定制指令用戶指南

         Nios II定制指令用戶指南:With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.

    標(biāo)簽: Nios 定制 指令 用戶

    上傳時(shí)間: 2013-10-12

    上傳用戶:kang1923

  • Nios II 系列處理器配置選項(xiàng)

        Nios II 系列處理器配置選項(xiàng):This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

    標(biāo)簽: Nios II 列處理器

    上傳時(shí)間: 2015-01-01

    上傳用戶:mahone

  • XAPP694-從配置PROM讀取用戶數(shù)據(jù)

    This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.

    標(biāo)簽: XAPP PROM 694 讀取

    上傳時(shí)間: 2013-10-09

    上傳用戶:guojin_0704

  • XAPP452-Spartan-3高級(jí)配置架構(gòu)

    This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.

    標(biāo)簽: Spartan XAPP 452 架構(gòu)

    上傳時(shí)間: 2013-11-16

    上傳用戶:qingdou

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