MIMO(Multiple-Input Multiple-Out-put)系統是一項運用于802.11n的核心技術。本篇文章全面介紹了MIMO系統多天線技術。
上傳時間： 2013-05-23
上傳用戶：LSPSL
電路連接 由于數碼管品種多樣，還有共陰共陽的，下面我們使用一個數碼管段碼生成器（在文章結尾） 去解決不同數碼管的問題： 本例作者利用手頭現有的一位不知品牌的共陽數碼管：型號D5611 A/B，在Eagle 找了一個 類似的型號SA56-11，引腳功能一樣可以直接代換。所以下面電路圖使用SA56-11 做引腳說明。 注意： 1. 將數碼管的a~g 段，分別接到Arduino 的D0~D6 上面。如果你手上的數碼管未知的話，可以通過通電測量它哪個引腳對應哪個字段，然后找出a~g 即可。 2. 分清共陰還是共陽。共陰的話，接220Ω電阻到電源負極；共陽的話，接220Ω電阻到電源+5v。 3. 220Ω電阻視數碼管實際工作亮度與手頭現有原件而定，不一定需要準確。 4. 按下按鈕即停。 源代碼 由于我是按照段碼生成器默認接法接的，所以不用修改段碼生成器了，直接在段碼生成器選擇共陽極，再按“自動”生成數組就搞定。 下面是源代碼，由于偷懶不用寫循環，使用了部分AVR 語句。 PORTD 這個是AVR 的端口輸出控制語句，8 位對應D7~D0，PORTD=00001001 就是D3 和D0 是高電平。 PORTD = a;就是找出相應的段碼輸出到D7~D0。 DDRD 這個是AVR 語句中控制引腳作為輸出/輸入的語句。DDRD = 0xFF;就是D0~D7 全部 作為輸出腳了。 ARDUINO CODECOPY /* Arduino 單數碼管骰子 Ansifa 2011-12-28 */ //定義段碼表，表中十個元素由LED 段碼生成器生成，選擇了共陽極。 inta[10] = {0xC0, 0xF9, 0xA4, 0xB0, 0x99, 0x92, 0x82, 0xF8, 0x80, 0x90}; voidsetup() { DDRD = 0xFF; //AVR 定義PortD 的低七位全部用作輸出使用。即0xFF=B11111111對 應D7~D0 pinMode(12, INPUT); //D12用來做骰子暫停的開關 } voidloop() { for(int i = 0; i < 10; i++) { //將段碼輸出PortD 的低7位，即Arduino 的引腳D0~D6，這樣需要取出PORTD 最高位，即 D7的狀態，與段碼相加，之后再輸出。 PORTD = a[i]; delay(50); //延時50ms while(digitalRead(12)) {} //如果D12引腳高電平，則在此死循環,暫停LED 跑 動 } }
上傳時間： 2013-10-15
上傳用戶：baitouyu
Linear Technology’s high performance battery management ICsenable long battery life and run time, while providing precision charging control, constantstatus monitoring and stringent battery protection. Our proprietary design techniques seamlesslymanage multiple input sources while providing small solution footprints, faster charging and100% standalone operation. Battery and circuit protection features enable improved thermalperformance and high reliability operation.
上傳時間： 2013-10-13
上傳用戶：yyq123456789
The PAM2862 is a continuous mode inductivestep-down converter, designed for driving singleor multiple series connected LEDs efficientlyfrom a voltage source higher than the LEDvoltage. The device operates from an inputupply between 6V and 30V and provides anexternally adjustable output current of up to 1A.Depending upon supply voltage and externalcomponents, this can provide up to 24 watts ofoutput power.
上傳時間： 2013-11-16
上傳用戶：司令部正軍級
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標簽： 4channel multiple 9544A 9544
上傳時間： 2014-12-28
上傳用戶：潛水的三貢
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上傳時間： 2014-11-22
上傳用戶：xcy122677
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
多遠程二極管溫度傳感器-Design Considerations for pc thermal management Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product performance and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall performance of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-programmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
標簽： Considerat Design 遠程 二極管
上傳時間： 2014-12-21
上傳用戶：ljd123456
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上傳時間： 2013-10-10
上傳用戶：geshaowei
