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NC-VHDL

VHDL復習資料

VHDL復習資料，復習資料，有源代碼

標簽： VHDL

上傳時間： 2013-11-23

上傳用戶：水中浮云
《VHDL實用教程》完整版

VHDL入門者值得學習!

標簽： VHDL 實用教程

上傳時間： 2013-11-06

上傳用戶：zhangfx728
VHDl實用教程(潘_松_王國棟_編著)

VHDL教程

標簽： VHDl 實用教程

上傳時間： 2015-01-01

上傳用戶：weiwolkt
vhdl 與數字電路設計

VHDL程序講解，配合實例，適合初學者，大學期間可用

標簽： vhdl 數字電路設計

上傳時間： 2013-12-30

上傳用戶：米米陽123
XAPP105 - CPLD VHDL介紹

This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.

標簽： XAPP CPLD VHDL 105

上傳時間： 2013-11-21

上傳用戶：gtf1207
The VHDL Cookbook (VHDL編碼書籍)

The VHDL Cookbook是是VHDL編碼書籍。

標簽： VHDL Cookbook The 編碼

上傳時間： 2013-11-19

上傳用戶：lixqiang
US Navy VHDL Modelling Guide

This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

標簽： Modelling Guide Navy VHDL

上傳時間： 2013-11-20

上傳用戶：pzw421125
PLD Programming Using VHDL

本文詳細討論了VHDL語句對PLD設計的影響和設計經驗，經典文章，值得仔細閱讀消化。,PLD Programming Using VHDL

標簽： Programming Using VHDL PLD

上傳時間： 2013-10-14

上傳用戶：www240697738
VHDL,Verilog,System verilog比較

本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

標簽： Verilog verilog System VHDL

上傳時間： 2014-03-03

上傳用戶：zhtzht
基于CPLD的VHDL語言數字鐘(含秒表)設計

利用一塊芯片完成除時鐘源、按鍵、揚聲器和顯示器（數碼管）之外的所有數字電路功能。所有數字邏輯功能都在CPLD器件上用VHDL語言實現。這樣設計具有體積小、設計周期短（設計過程中即可實現時序仿真）、調試方便、故障率低、修改升級容易等特點。本設計采用自頂向下、混合輸入方式（原理圖輸入—頂層文件連接和VHDL語言輸入—各模塊程序設計）實現數字鐘的設計、下載和調試。

標簽： CPLD VHDL 語言數字

上傳時間： 2013-10-24

上傳用戶：古谷仁美