This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned OFF and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時間： 2013-11-11
上傳用戶：gundamwzc
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-OFF. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時間： 2014-01-24
上傳用戶：15527161163
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an OFF-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時間： 2013-11-01
上傳用戶：wojiaohs
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care OFF if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-23
上傳用戶：我干你啊
Abstract: As industrial control systems (ICSs) have become increasingly connected and use more OFF-the-shelfcomponents, new vulnerabilities to cyber attacks have emerged. This tutorial looks at three types of ICSs:programmable logic controllers (PLCs), supervisory control and data acquisition (SCADA) systems, anddistributed control systems (DCSs), and then discusses security issues and remedies. This document alsoexplains the benefits and limitations of two cryptographic solutions (digital signatures and encryption) andelaborates on the reasons for using security ICs in an ICS to support cryptography.
標(biāo)簽： 工業(yè)系統(tǒng) 安全問題
上傳時間： 2013-10-09
上傳用戶：woshinimiaoye
Have you had the exasperating experience of a laptop orPDA defi antly not responding to your commands? Youfrantically press key after key, but to no avail. As hopeturns to anger (but just before you throw the company’slaptop through the window) you slam your fi nger againstthe on/OFF power button. Ten seconds later, your laptopfi nally surrenders and the screen goes black in a highpitched whimper.
標(biāo)簽： 427 DN 開關(guān)控制器 故障保護(hù)
上傳時間： 2013-12-10
上傳用戶：Vici
QX5305 是一款高效率，穩(wěn)定可靠的高亮度LED燈驅(qū)動控制IC，內(nèi)置高精度比較器，OFF-time控制電路，恒流驅(qū)動控制電路等，特別適合大功率，多個高亮度LED燈串恒流驅(qū)動。 QX5305采用固定OFF-time控制工作方式，其工作頻率可高達(dá)2.5MHz，可使外部電感和濾波電容、體積減少，效率提高。 在DIM腳加PWM信號，可調(diào)節(jié)LED燈的亮度。 通過調(diào)節(jié)外置的電阻，能控制高亮度LED燈的驅(qū)動電流，使LED燈亮度達(dá)到預(yù)期恒定亮度，流過高亮度LED燈的電流可從幾毫安到2安培變化。 方框圖： 管腳排列圖： QX5305的特性 可編程驅(qū)動電流，最高可達(dá)2A 高效率：最高達(dá)95% 寬輸入電壓范圍：2.5V~36V 高工作頻率：2.5MHz 工作頻率可調(diào)：500KHz~2.5MHz 驅(qū)動LED燈功能強(qiáng)：LED燈串可從1個到幾十個LED高亮度燈 亮度可調(diào)：通過EN端PWM，調(diào)節(jié)LED燈亮度 QX5305應(yīng)用范圍 干電池供電LED燈串 LED燈杯 RGB大顯屏高亮度LED燈 平板顯示器LED背光燈 恒流充電器控制 通用恒流源。 工作原理簡述： QX5305 采用峰值電流檢測和固定OFF-time控制方式。片內(nèi)的R-S觸發(fā)器分別由OFF-time定時器置位和CS比較器、FB比較復(fù)位，它控制外部MOSFET管并和功率電感 L、LED、肖特基二極管共同構(gòu)成一個自振蕩的，連續(xù)電感電流模式的升壓型恒流LED驅(qū)動電路（參見圖1）。 除了固定OFF-time控制這點外，QX5305的工作方式和普通的電流模式PWM控制型DC/DC升壓電路非常相似。當(dāng)工作在連續(xù)電流模式下時，流過功率電感的電流IL如圖所示：
上傳時間： 2013-10-26
上傳用戶：TF2015
TIMER.ASM ********* [ milindhp@tifrvax.tifr.res.in ] Set Processor configuration word as = 0000 0000 1010 b. a] -MCLR tied to VDD (internally). b] Code protection OFF. c] WDT disabled. d] Internal RC oscillator [4 MHZ].
標(biāo)簽： configuration Processor milindhp tifrvax
上傳時間： 2015-05-24
上傳用戶：wqxstar
The Hopfield model is a distributed model of an associative memory. Neurons are pixels and can take the values of -1 (OFF) or +1 (on). The network has stored a certain number of pixel patterns. During a retrieval phase, the network is started with some initial configuration and the network dynamics evolves towards the stored pattern which is closest to the initial configuration.
標(biāo)簽： model distributed associative Hopfield
上傳時間： 2015-06-17
上傳用戶：l254587896
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-OFF Flag
標(biāo)簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
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