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OPTIMIZATION

  • this modified PSO algorithm can solve for constrained OPTIMIZATION problem

    this modified PSO algorithm can solve for constrained OPTIMIZATION problem

    標簽: OPTIMIZATION constrained algorithm modified

    上傳時間: 2017-09-12

    上傳用戶:nanshan

  • Differential Evolution for single variable function OPTIMIZATION!

    Differential Evolution for single variable function OPTIMIZATION!

    標簽: Differential OPTIMIZATION Evolution function

    上傳時間: 2017-09-13

    上傳用戶:lhc9102

  • quantized control via locational OPTIMIZATION

    quantized control via locational OPTIMIZATION

    標簽: OPTIMIZATION locational quantized control

    上傳時間: 2017-09-28

    上傳用戶:417313137

  • Transition-Time OPTIMIZATION for Switched-Mode Dynamical Systems

    Transition-Time OPTIMIZATION for Switched-Mode Dynamical Systems

    標簽: Transition-Time Switched-Mode OPTIMIZATION Dynamical

    上傳時間: 2017-09-28

    上傳用戶:xinyuzhiqiwuwu

  • OPTIMIZATION Modelling A Practical Approach

    OPTIMIZATION Modelling A Practical Approach Ruhul A. Sarker Charles S. Newton

    標簽: 數學建模

    上傳時間: 2016-02-15

    上傳用戶:jh442755_1

  • Design Compiler OPTIMIZATION Reference Manual

    Design Compiler OPTIMIZATION Reference Manual

    標簽: OPTIMIZATION Reference Compiler Design Manual

    上傳時間: 2019-04-03

    上傳用戶:zsx097

  • Telecommunications+OPTIMIZATION+heuristics

    Each of us is interested in OPTIMIZATION, and telecommunications. Via several meetings, conferences, chats, and other opportunities, we have discovered these joint interests and decided to put together this book.

    標簽: Telecommunications OPTIMIZATION heuristics

    上傳時間: 2020-06-01

    上傳用戶:shancjb

  • Creating Safe State Machines(Mentor)

      Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the OPTIMIZATION is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.

    標簽: Creating Machines Mentor State

    上傳時間: 2013-10-08

    上傳用戶:wangzhen1990

  • SJA1000 Stand-alone CAN contro

    The Controller Area Network (CAN) is a serial, asynchronous, multi-master communication protocol forconnecting electronic control modules, sensors and actuators in automotive and industrial applications.With the SJA1000, Philips Semiconductors provides a stand-alone CAN controller which is more than a simpleeplacement of the PCA82C200.Attractive features are implemented for a wide range of applications, supporting system OPTIMIZATION, diagnosisand maintenance.

    標簽: Stand-alone contro 1000 SJA

    上傳時間: 2013-11-18

    上傳用戶:yxgi5

  • Xilinx UltraScale:新一代架構滿足您的新一代架構需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-OPTIMIZATION with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標簽: UltraScale Xilinx 架構

    上傳時間: 2013-11-13

    上傳用戶:瓦力瓦力hong

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