there is additional code code required to create a log window for output
標簽： code additional required create
上傳時間： 2016-12-01
上傳用戶：baitouyu
在C++中open一個output file有兩種方式，一種是使用member function open( )，另外一種是使用constructor給予檔案名稱和open mode。今若欲open一個名為client.dat的output file，試分別寫出該兩種方式open此檔案的statements.(包括include header file，物件的宣告，open指令等)
上傳時間： 2016-12-21
上傳用戶：wxhwjf
Implement a phone book system for employees of a company. Your program will output the following menu (1) Enter an employee and a phone pair to the system (2) Lookup an employee s phone number (3) Find out who is/are the person(s) of a given number (4) How many people are currently in the system (5) Delete an employee from the system (6) Output all employees name‐phone pair (7) How many phone numbers total in the current system (8) Quit When
標簽： Implement employees following company
上傳時間： 2013-12-17
上傳用戶：zhangliming420
Audio output from sound file for MCU.
上傳時間： 2013-12-23
上傳用戶：windwolf2000
msp430心電儀程序代碼 ............\Heart rate ............\Heart rate with DAC output ............\Heart rate with EKG Demo ............\mul.s43（需要與上面三個之一配合使用）
上傳時間： 2016-12-24
上傳用戶：曹云鵬
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs and an initial network ％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the ％ network with backpropagation. ％ ％ The activation functions must be either linear or tanh. The network ％ architecture is defined by the matrix NetDef consisting of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer. ％
標簽： back-propagation corresponding input-output algorithm
上傳時間： 2016-12-27
上傳用戶：exxxds
Produces a matrix of derivatives of network output w.r.t. ％ each network weight for use in the functions NNPRUNE and NNFPE.
標簽： network w.r.t. derivatives Produces
上傳時間： 2013-12-18
上傳用戶：sunjet
verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位
標簽： output look-ahead summation carryout
上傳時間： 2017-01-07
上傳用戶：yyq123456789
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0
標簽： output look-ahead carryout verilog
上傳時間： 2014-12-06
上傳用戶：ls530720646
verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y
標簽： input array_multiplier verilog product
上傳時間： 2014-01-04
上傳用戶：wxhwjf
